AD7457 Ver la hoja de datos (PDF) - Analog Devices
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AD7457 Datasheet PDF : 20 Pages
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AD7457
–50
–60
–70
200Ω
–80
–90
TA = 25°C
100Ω
10Ω
62Ω
10
20
30
40
50
INPUT FREQUENCY (kHz)
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
Figure 21 shows a graph of THD vs. analog input frequency for
various supply voltages, while sampling at 100 kSPS with an
SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
–50
TA = 25°C
–55
–60
–65
–70
–75
–80
–85
–90
10
VDD = 2.7V
VDD = 3.6V
VDD = 4.75V
VDD = 5.25V
20
30
INPUT FREQUENCY (kHz)
40
50
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
DIGITAL INPUTS
The digital inputs applied to the AD7457 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied, that is, CS and SCLK, can go to 7 V and are not
restricted by the VDD + 0.3 V limits as on the analog input.
The main advantage of the inputs not being restricted to the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to VDD.
REFERENCE SECTION
An external source is required to supply the reference to the
AD7457. This reference input can range from 100 mV to VDD.
The specified reference is 2.50 V for the power supply range
2.70 V to 5.25 V. Errors in the reference source result in gain
errors in the AD7457 transfer function. A capacitor of at least
0.33 µF should be placed on the VREF pin. Suitable reference
sources for the AD7457 include the AD780 and the ADR421.
Figure 22 shows a typical connection diagram for the VREF pin.
VDD
0.1µF
10µF
AD780
NC
0.1µF
1
OPSEL 8 NC
2 VIN
7 NC
3 TEMP VOUT 6 2.5V
4 GND TRIM 5 NC
VDD
AD74571
VREF
0.33µF
NC = NO CONNECT
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 22. Typical VREF Connection Diagram for VDD = 5 V
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface
of the AD7457. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversions.
The falling edge of CS powers up the AD7457 and also puts the
track-and-hold into track. Power-up time is 1 µs minimum and,
in this time, the device also acquires the analog input signal. CS
must remain low for the duration of power-up. The rising edge
of CS initiates the conversion process, puts the track-and-hold
into hold mode, and takes the serial data bus out of three-state.
The conversion requires 16 SCLK cycles to complete.
On the sixteenth SCLK falling edge, after the time t8, the serial
data bus goes back into three-state and the device automatically
enters full power-down. It remains in power-down until the
next falling edge of CS. For specified performance, the through-
put rate should not exceed 100 kSPS, which means that there
should be no less than 10 µs between consecutive CS falling
edges.
The conversion result from the AD7457 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7457 consists of four leading zeros, followed by the 12 bits of
conversion data that are provided MSB first. The output coding
is straight (natural) binary.
Sixteen serial clock cycles are, therefore, required to perform a
conversion and to access data from the AD7457. A rising edge
of CS provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out on
the subsequent SCLK falling edges, beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
after CS has gone high provides the second leading zero. The
final bit in the data transfer, before the device goes into power-
down, is valid on the sixteenth falling edge of SCLK, having
been clocked out on the previous (fifteenth) falling edge.
Rev. A | Page 13 of 20
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