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AD9510

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

AD9510

CLOCK OUTPUTS

Table 3.

Parameter

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2, OUT3; Differential

Output Frequency

Output High Voltage (VOH)

Output Low Voltage (VOL)

Output Differential Voltage (VOD)

LVDS CLOCK OUTPUTS

OUT4, OUT5, OUT6, OUT7; Differential

Output Frequency

Differential Output Voltage (VOD)

Delta VOD

Output Offset Voltage (VOS)

Delta VOS

Short-Circuit Current (ISA, ISB)

CMOS CLOCK OUTPUTS

OUT4, OUT5, OUT6, OUT7

Output Frequency

Output Voltage High (VOH)

Output Voltage Low (VOL)

Min

Typ

Max

Unit Test Conditions/Comments

Termination = 50 Ω to VS − 2 V

Output level 3Ch (3Dh) (3Eh) (3Fh)<3:2> = 10b

1200 MHz See Figure 21

VS − 1.22 VS − 0.98 VS − 0.93 V

VS − 2.10 VS − 1.80 VS − 1.67 V

660

810

965 mV

Termination = 100 Ω differential; default

Output level 40h (41h) (42h) (43h)<2:1> = 01b

3.5 mA termination current

800 MHz See Figure 22

250

360

450 mV

25

mV

1.125

1.23

1.375 V

25

mV

14

24

mA Output shorted to GND

VS − 0.1

Single-ended measurements;

B outputs: inverted, termination open

250 MHz With 5 pF load each output; see Figure 23

V

@ 1 mA load

0.1

V

@ 1 mA load

Rev. A | Page 6 of 60

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