AD9510 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Lista de partido

AD9510

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

AD9510

Parameter

DELAY ADJUST4

Shortest Delay Range5

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Longest Delay Range5

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Delay Variation with Temperature

Long Delay Range, 10 ns6

Zero Scale

Full Scale

Short Delay Range, 1 ns6

Zero Scale

Full Scale

Min Typ

0.05 0.36

0.72 1.12

0.5

0.8

0.20 0.57

9.0 10.2

0.3

0.6

Max Unit Test Conditions/Comments

OUT5 (OUT6); LVDS and CMOS

35h (39h) <5:1> 11111b

0.68 ns

36h (3Ah) <5:1> 00000b

1.51 ns

36h (3Ah) <5:1> 11111b

LSB

LSB

35h (39h) <5:1> 00000b

0.95 ns

36h (3Ah) <5:1> 00000b

11.6 ns

36h (3Ah) <5:1> 11111b

LSB

LSB

0.35

−0.14

0.51

0.67

ps/°C

ps/°C

ps/°C

ps/°C

1 The measurements are for CLK1. For CLK2, add approximately 25 ps.

2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

4 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

5 Incremental delay; does not include propagation delay.

6 All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. A | Page 8 of 60

Share Link: