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RTL8139C

REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8139C(L)

6.12 Media Status Register

(Offset 0058h, R/W)

This register allows configuration of a variety of device and PHY options, and provides PHY status information.

Bit

R/W

Symbol

Description

7

R/W

TXFCE/

Tx Flow Control Enable: The flow control is valid in full-duplex

LdTXFCE

mode only. This register’s default value comes from 93C46 (93C56).

RTL8139C(L)

ANE = 1

ANE = 1

ANE = 1

ANE = 0 &

full-duplex mode

ANE = 0 &

half-duplex mode

Remote

NWAY FLY mode

NWAY mode only

No NWAY

-

-

TXFCE/LdTXFCE

R/O

R/W

R/W

R/W

invalid

NWAY FLY mode: NWAY with flow control capability

NWAY mode only: NWAY without flow control capability

6

R/W

RXFCE

RX Flow control Enable: The flow control is enabled in full-duplex

mode only. The default value comes from 93C46 (93C56).

5

-

-

Reserved

4

R

Aux_Status Aux. Power present Status:

1: The Aux. Power is present.

0: The Aux. Power is absent.

The value of this bit is fixed after each PCI reset.

3

R

SPEED_10

Speed: Set, when current media is 10 Mbps mode. Reset, when current

media is 100 Mbps mode.

2

R

LINKB

Inverse of Link status: 0 = Link OK. 1 = Link Fail.

1

R

TXPF

Transmit Pause Flag: Set when the RTL8139C(L) sends pause packet.

Reset when the RTL8139C(L) sends timer done packet.

0

R

RXPF

Receive Pause Flag: Set when the RTL8139C(L) is in backoff state

because a pause packet received. Reset when pause state is clear.

6.13 CONFIG 3: Configuration Register3

(Offset 0059h, R/W)

Bit

R/W

Symbol

Description

7

R

GNTSel

Gnt Select: Select the Frame’s asserted time after the Grant signal has

been asserted. The Frame and Grant are the PCI signals.

1: Delay one clock from GNT assertion

0: No delay

6

R/W

PARM_En

Parameter Enable: (These parameters are used in 100Mbps mode)

Setting to 0 and 9346CR register EEM1=EEM0=1 enable the

PHY1_PARM, PHY2_PARM, TW_PARM be written via software.

Setting to 1 will allow parameters auto-loaded from 93C46 (93C56)

and disable writing to PHY1_PARM, PHY2_PARM and TW_PARM

registers via software. The PHY1_PARM, PHY2_PARM, and

TW_PARM can be auto-loaded from EEPROM in this mode. The

parameter auto-load process is executed every time when the Link is

OK in 100Mbps mode.

2002/01/10

22

Rev.1.4

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