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AD9577

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

Analog Devices

AD9577 Datasheet PDF : 44 Pages

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AD9577

Parameter

Phase Noise (106.25 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (156.25 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

1 x indicates either 0 or 1 for any given test condition.

Data Sheet

Min Typ

−118

−127

−149

−156

−157

−115

−124

−146

−155

−117

−122

−123

−148

−156

−105

−110

−136

−150

−117

−122

−123

−146

−155

−105

−110

−134

−149

−150

−117

−122

−123

−147

−155

Max Unit

dBc/Hz

Test Conditions/Comments1

Na = 102, Vx = 4, Dx = 6, fPFD = 25 MHz

Na = 100, Vx = 4, Dx = 4, fPFD = 25 MHz

Na = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Na = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz

Na = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Na = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz

Na = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Rev. A | Page 4 of 44

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