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AD9577

Clock Generator with Dual PLLs, Spread Spectrum, and Margining

Analog Devices

AD9577 Datasheet PDF : 44 Pages

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AD9577

Parameter

Phase Noise (156.25 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

1 x indicates either 2 or 3 for any given test condition.

Data Sheet

Min Typ Max

−113

−119

−123

−145

−154

−155

−112

−118

−126

−147

−155

−156

−100

−106

−112

−134

−149

−150

−113

−118

−126

−145

−154

−155

−101

−106

−112

−133

−148

−150

−113

−118

−126

−146

−155

Unit

dBc/Hz

Test Conditions/Comments1

Nb = 100, Vx = 4, Dx = 4, fPFD = 25 MHz

Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Nb = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz

Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Nb = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz

Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz

Rev. A | Page 8 of 44

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