EVAL-ADF4193EB1(RevB) Ver la hoja de datos (PDF) - Analog Devices
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EVAL-ADF4193EB1 Datasheet PDF : 28 Pages
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ADF4193
MOD/R REGISTER (R1)
4-BIT RF
R COUNTER
12-BIT MODULUS
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F5 F4
0
F2 F1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7
DB8
M6
DB7
M5
DB6
M4
DB5
M3
DB4
M2
DB3 DB2 DB1 DB0
M1 C3 (0) C2 (0) C1 (1)
F4 REF/2
0 DISABLE
1 ENABLE
F2 PRESCALER
0 4/5
1 8/9
F5 CP ADJ
0 NOMINAL
1 ADJUSTED
F1 DOUBLER ENABLE
0 DOUBLER DISABLED
1 DOUBLER ENABLED
M12 M11 M10
M3
M2
0
0
0
.......... 1
0
0
0
0
.......... 1
1
0
0
0
.......... 1
1
.
.
.
.......... .
.
.
.
.
.......... .
.
.
.
.
.......... .
.
1
1
1
.......... 1
0
1
1
1
.......... 1
0
1
1
1
.......... 1
1
1
1
1
.......... 1
1
M1 INTERPOLATOR MODULUS VALUE (MOD)
1
13
0
14
1
15
.
.
.
.
.
.
0
4092
1
4093
0
4094
1
4095
R4
R3
0
0
0
0
0
0
0
1
.
.
.
.
.
.
1
1
1
1
1
1
1
1
R2
R1
RF R COUNTER DIVIDE RATIO
0
1
1
1
0
2
1
1
3
0
0
4
.
.
.
.
.
.
.
.
.
0
0
12
0
1
13
1
0
14
1
1
15
Figure 30. MOD/R Register (R1)
This register is used to set the PFD reference frequency and the
channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the MOD, R
counter, REF/2, CP ADJ, and doubler enable bits are double
buffered. They do not take effect until the next write to R0
(FRAC/INT register) is complete.
Control Bits
With C3, C2, and C1 set to 0, 0, 1, respectively, the MOD/R
register (R1) is programmed.
CP ADJ
When this bit is set to 1, the charge pump current is scaled up
25% from its nominal value on the next write to R0. When this
bit is set to 0, the charge pump current stays at its nominal value
on the next write to R0. See the Programming section for more
information on how this feature can be used.
REF/2
Setting this bit to 1 inserts a divide-by-2, toggle flip-flop
between the R counter and PFD, which extends the maximum
REFIN input rate.
Reserved Bit
Reserved Bit DB21 must be set to 0.
Doubler Enable
Setting this bit to 1 inserts a frequency doubler between REFIN
and the 4-bit R counter. Setting this bit to 0 bypasses the
doubler.
4-Bit RF R Counter
It allows the REFIN frequency to be divided down to produce the
reference clock to the PFD. All integer values from 1 to 15 are
allowed. See the Worked Example section.
12-Bit Interpolator Modulus
For a given PFD reference frequency, the fractional denomina-
tor or modulus sets the channel step resolution at the RF
output. All integer values from 13 to 4095 are allowed. See the
Programming section for additional information and guidelines
for selecting the value of MOD.
Rev. B | Page 16 of 28
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