EVAL-ADF4193EB1(RevB) Ver la hoja de datos (PDF) - Analog Devices
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EVAL-ADF4193EB1 Datasheet PDF : 28 Pages
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ADF4193
CHARGE PUMP REGISTER (R4)
RESERVED
9-BIT TIMEOUT COUNTER
TIMER
SELECT
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
C9 C8 C7 C6 C5 C4 C3 C2 C1 F2 F1 C3 (1) C2 (0) C1 (0)
C9
C8
C7
C3
C2
0
0
0
.......... 0
0
0
0
0
.......... 0
0
0
0
0
.......... 0
1
0
0
0
.......... 0
1
.
.
.
.......... .
.
.
.
.
.......... .
.
.
.
.
.......... .
.
1
1
1
.......... 1
0
1
1
1
.......... 1
0
1
1
1
.......... 1
1
1
1
1
.......... 1
1
Figure 33. Charge Pump Register (R4)
F2 F1 TIMER SELECT
0 0 SW1/SW2
0 1 SW3
1 0 ICP
1 1 NOT USED
C1
TIMEOUT COUNTER xPFD CYCLES DELAY µs1
0
0
1
1
0
2
1
3
.
.
.
.
.
.
0
508
1
509
0
510
1
511
0
4
8
12
.
.
.
2032
2036
2040
2044
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
1DELAY WITH 26MHz PFD
Reserved Bits
Bit DB23 to Bit DB14 are reserved and should be set to hex
code 001 for normal operation.
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency, therefore, their time delay scales with the PFD
frequency according to
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
For example, if 35 were loaded with timer select (00) with a
13 MHz PFD, then SW1/SW2 would be switched after
(35 × 4)/13 MHz = 10.8 μs
Timer Select
These two address bits select the timeout counter to be
programmed. Note that to set up the ADF4193 correctly
requires setup of these three timeout counters; therefore, three
writes to this register are required in the initialization sequence.
Table 6 shows example values for a GSM Tx synthesizer with a
60 kHz final loop BW. See the Applications section for more
information.
Table 6. Recommended Values for a GSM Tx LO
Time (μs) with
Timer Select Timeout Counter Value PFD = 13 MHz
10
ICP
28
8.6
01
SW1/2
35
10.8
00
SW3
35
10.8
On each write to R0, the timeout counters start. Switch SW3
closes until the SW3 counter times out. Similarly, switches
SW1/SW2 close until the SW1/SW2 counter times out. When
the ICP counter times out, the charge pump current is ramped
down from 64× to 1× in six binary steps. It is recommended
that the SW1, SW2, and SW3 timeout counter values are set
equal to the ICP timeout counter value plus 7, as in the example
of Table 6.
Rev. B | Page 19 of 28
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