ADF4193(RevB) Ver la hoja de datos (PDF) - Analog Devices
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ADF4193 Datasheet PDF : 28 Pages
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PHASE REGISTER (R2)
12-BIT PHASE
CONTROL
BITS
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3 (0) C2 (1) C1 (0)
ADF4193
P12 P11 P10
P3
0
0
0
.......... 0
0
0
0
.......... 0
0
0
0
.......... 0
.
.
.
.......... .
.
.
.
.......... .
.
.
.
.......... .
1
1
1
.......... 1
1
1
1
.......... 1
1
1
1
.......... 1
1
1
1
.......... 1
P2
P1
PHASE VALUE1
0
0
0
0
1
1
1
0
2
.
.
.
.
.
.
.
.
.
0
0
4092
0
1
4093
1
0
4094
1
1
4095
10 = < PHASE VALUE < MOD
Figure 31. Phase Register (R2)
12-Bit Phase
The phase word sets the seed value of the Σ-Δ modulator. It can
be programmed to any integer value from 0 to MOD. As the
phase word is swept from 0 to MOD, the phase of the VCO
output sweeps over a 360° range in steps of 360°/MOD.
Note that the phase bits are double buffered. They do not take
effect until the LE of the next write to R0 (FRAC/INT register).
Therefore, if it is desired to change the phase of the VCO output
frequency, it is necessary to rewrite the INT and FRAC values to
R0, following the write to R2.
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
If it is desired to keep the output at the same phase offset with
respect to the reference, each time that particular output
frequency is programmed, then the interval between writes to
R0 must be an integer multiple of MOD reference cycles.
If it is desired to keep the outputs of two ADF4193-based
synthesizers phase coherent with each other, but not necessarily
with their common reference, then it is only required to ensure
that the write to R0 on both chips is performed during the same
reference cycle. The interval between R0 writes in this case does
not have to be an integer multiple of the MOD cycles.
Reserved Bit
The reserved bit, Bit DB15, should be set to 0.
Rev. B | Page 17 of 28
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