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ADF4193 Datasheet PDF : 32 Pages
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ADF4193
Data Sheet
Parameter
SW1, SW2, and SW3
RON (SW1 and SW2)
RON SW3
NOISE CHARACTERISTICS
Output
900 MHz4
1800 MHz5
Phase Noise
Normalized Phase Noise
Floor (PNSYNTH)6
Normalized 1/f Noise (PN1_f)7
B Version1
65
75
−108
−102
−216
−110
C Version2
65
75
−108
−102
−216
−110
Unit
Ω typ
Ω typ
Test Conditions/Comments
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
At 5 kHz offset and 26 MHz PFD frequency
At 5 kHz offset and 13 MHz PFD frequency
At VCO output with dither off, PLL loop
bandwidth = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
1 Operating temperature range is from −40°C to +85°C.
2 Operating temperature range is from −40°C to +105°C
3 The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value.
4 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz.
5 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N).
7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,
fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V ± 10%, VP1, VP2 = 5 V ± 10%, VP3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm referred to
50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit (B Version)1
10
10
10
15
15
10
15
Limit (C Version) 2
10
10
10
15
15
10
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
1 Operating temperature is from −40°C to +85°C.
2 Operating temperature is from −40°C to +105°C.
CLK
DATA
LE
LE
DB23
(MSB)
t2
t3
DB22
t1
t4
t5
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Figure 2. Timing Diagram
Rev. F | Page 4 of 32
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