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AIC1571

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

Analog Intergrations 

AIC1571

BLOCK DIAGRAM

VSEN

PGOOD

VCC

FB3

GATE3

GATE2

FB2

VIN2

FAULT

+

+

0.3V

+

+

-

-

1.26V

VCC

VIN2

OCSET

INHiBIT

POWER

ON RESET

LUV

VCC

SOFT

START

10µA

4V

5V

FAULT

LOGIC &

LATCH

OFF

70K

70K

70K

70K

70K

5 BIT TTL D/A

CONVERTER

(DAC)

110%

+

90%

+

115%

+

200µA

OC1

+

+

ERROR

AMP

OV

+

GATE CONTROL

PWM COMP

OSCILLATOR

SS

VID0 VID1 VID2 VID3 VID4

FB1

COMP1 RT

VCC

VCC

OCSET

PHASE

UGATE

LGATE

PGND

GND

PIN DESCRIPTIONS

Pin 1: VCC:

The chip power supply pin. It al-

so provides the gate bias charge

for all the MOSFETs controlled

by the IC. Recommended supply

voltage is 12V.

Pin 2:

Pin 3:

Pin 4:

Pin 5:

Pin 6:

VID4:

VID3:

VID2:

VID1:

VID0:

5bit DAC voltage select pin. TTL

inputs used to set the internal

voltage reference VDAC. When

left open, these pins are inter-

nally pulled up to 5V and provide

logic ones. The level of VDAC

sets the converter output voltage

as well as the PGOOD and OVP

thresholds.

Pin 7: PGOOD:

Pin 8: FAULT:

Table 1 specifies the VDAC volt-

age for the 32 combinations of

DAC inputs.

Power good indicator pin.

PGOOD is an open drain output.

This pin is pulled low when the

converter output is ±10% out of

the VDAC reference voltage and

the other outputs are below their

under-voltage thresholds. The

PGOOD output is open for VID

codes that inhibit operation. See

Table 1.

This pin is low during normal op-

eration, but it is pulled to VCC in

the event of an over-voltage or

over-current condition.

8

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