AK4563A Ver la hoja de datos (PDF) - Asahi Kasei Microdevices
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AK4563A Datasheet PDF : 39 Pages
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ASAHI KASEI
[AK4563A]
OPERATION OVERVIEW
System Clock Input
The clocks which are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC or DAC is in operation. If these
clocks are not provided, the AK4563A may draw excess current and it is not possible to operate properly because utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4563A should be in the power-down
mode.
System Reset
AK4563A should be reset once by bringing PDN pin “L” upon power-up. After the system reset operation, the all internal
AK4563A registers are initial value.
The initial cycle is 4128/fs=86ms@fs=48kHz. During offset calibration, the ADC digital data outputs of both channels
are forced to a 2’s compliment “0”. Output data of settles data equivalent for analog input signal after offset calibration.
This cycle is not for DAC.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
MS0067-E-02
- 11 -
2004/12
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