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AK4563A

Low Power 16bit 4ch ADC & 2ch DAC with ALC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4563A]

„ Control Register R/W Timing

The data on the 4 wires serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,

8bit). The transmitting data is output to each bit by “↓” of CCLK, the receiving data is latched by “↑” of CCLK. Writing

data becomes effective by “↑” of CSN. Reading data becomes Hi-z (Floating) by “↑” of CSN. CSN should be held to “H”

at no access. In case of connecting between CDTI and CDTO, the I/F can be also contolled by 3-wires.

CCLK always needs 16 edges of “↑” during CSN = “L”. Reading/Writing of the address except 00H ∼ 09H are inhibited.

Reading/Writing of the control registers by except op0 = op1 = “1” are invalid.

CSN

CCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CDTI

WRITE

CDTO

READ

CDTI

CDTO

op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7

“1” “1” “1”

Hi-Z

op0 op1 op2 A0 A1 A2 A3 A4

“1” “1” “0”

Hi-Z

D0 D1 D2 D3 D4 D5 D6 D7

Hi-Z

op0-op2: Op code (110:READ, 111:WRITE)

A0-A4: Register Address

D0-D7: Control data

Figure 13. Control Data Timing

MS0067-E-02

- 15 -

2004/12

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