AM79C978AKCW Ver la hoja de datos (PDF) - Advanced Micro Devices
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AM79C978AKCW Datasheet PDF : 256 Pages
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M
MAC 62, 63, 64
Magic Packet Mode 88
Magic Packet™ mode 1
Management Cycle Timing 224
Management Data Clock 26
Management Data Input/Output 26
Management Data Output Valid Delay Timing 231
Management Data Setup and Hold Timing 231
Management Interfaces 79
Manchester Encoder/Decoder 10
Master Abort 46, 48
Master Bus Interface Unit 39
Master Cycle Data Parity Error Response 48
Master Initiated Termination 45
MDC 26
MDC Waveform 230
MDIO 26
Media Access Controller (MAC) 1, 2
Media Access Management 64
Media Independent Interface 29
Medium Allocation 64
Microsoft OnNow 2
MII Interface 25
MII interface 2
MII Management Frames 31
MII Management Interface 30
MII Network Status Interface 30
MII Receive Interface 30
MII Transmit Interface 29
Miscellaneous Loopback Features 70
Mode 196
N
NAND Tree Circuitry 91
NAND Tree Circuitry (160 PQFP 91
NAND Tree Circuitry (160 PQFP) 91
NAND Tree Pin Sequence (144 TQFP) 92
NAND Tree Pin Sequence (160 PQFP) 92
NAND Tree Testing 91
NAND Tree Waveform 93
Network Interfaces 29
Network Port Manager 32
No SRAM Configuration 81
Non-Burst FIFO DMA Transfers 54
Non-Burst Read Transfer 40
Non-Burst Write Transfer 42
Normal and Tri-State Outputs 225
O
Offset 00h 99
Offset 02h 99
Offset 04h 100
Offset 06h 101
Offset 08h 102
Offset 09h 102
Offset 0Ah 102
Offset 0Bh 103
Offset 0Dh 103
Offset 0Eh 103
Offset 10h 103
Offset 14h 104
Offset 2Ch 104
Offset 2Eh 104
Offset 30h 105
Offset 34h 105
Offset 3Ch 105
Offset 3Dh 106
Offset 3Eh 106
Offset 3Fh 106
Offset 40h 106
Offset 41h 106
Offset 42h 106
Offset 44h 107
Offset 46h 108
Offset 47h 108
OnNow Functional Diagram 87
OnNow Pattern Match Mode 87
OnNow Wake-Up Sequence 86
Operating Ranges 217
Ordering Information 20
Other Data Registers 90
Outline of LAPP Flow B-1
Output and Float Delay Timing 219
Output Tri-State Delay Timing 227
Output Tri-state Delay Timing 227
Output Valid Delay Timing 227
P
PADR 196
PAR 22
Parity 22
Parity Error 22
Parity Error Response 37, 46
Pattern Match RAM 89
Pattern Match RAM (PMR) 87
PCI and JTAG Configuration Information 32
PCI Base-Class Register Offset 0Bh 103
PCI Bus Interface Pins - 3.3 V Signaling 217
PCI Bus Interface Pins - 5 V Signaling 217
PCI Bus Power Management Interface specification 2
PCI Capabilities Pointer Register 105
PCI Capability Identifier Register 106
PCI Command Register 100
PCI Command Register Offset 04h 100
PCI Configuration Registers 94, 98, 99, 204
PCI Configuration Space Layout 94
PCI Data Register 108
PCI Data Register Offset 47h 108
PCI Device ID Register 99
PCI Device ID Register Offset 02h 99
PCI Expansion ROM Base Address Register 105
PCI Header Type Register 103
PCI Header Type Register Offset 0Eh 103
PCI I/O Base Address Register 103
Index-6
Am79C978A
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