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AM79C978AKCW

PCnet™- Home Single-Chip 1/10 Mbps PCI Home Networking Controller

Advanced Micro Devices 

PCI I/O Base Address Register Offset 10h 103

PCI I/O Buffer Power (9 Pins) 27

PCI Interface 21

PCI Interrupt Line Register 105

PCI Interrupt Line Register Offset 3Ch 105

PCI Interrupt Pin Register 106

PCI Latency Timer Register 103

PCI MAX_LAT Register 106

PCI Memory Mapped I/O Base Address Register 104

PCI MIN_GNT Register 106

PCI Next Item Pointer Register 106

PCI Next Item Pointer Register Offset 41h 106

PCI PMCSR Bridge Support Extensions Register 108

PCI PMCSR Bridge Support Extensions Register Off-

set 46h 108

PCI Power Management Capabilities Register (PMC)

106

PCI Power Management Control/Status Register

(PMCSR) 107

PCI Programming Interface Register 102

PCI Programming Interface Register Offset 09h 102

PCI Revision ID Register 102

PCI Status Register 101

PCI Status Register Offset 06h 101

PCI Sub-Class Register 102

PCI Sub-Class Register Offset 0Ah 102

PCI Subsystem ID Register 104

PCI Subsystem Vendor ID Register 104

PCI Vendor ID Register 99

PCI Vendor ID Register Offset 00h 99

PECL 222

PERR 22

PHY Control and Management Block (PCM Block) 80

PHY Select Programming 157

PHY/MAC Interface 71

PHY_RST 26

PHYSICAL DIMENSIONS 232

Physical Layer Devices (Multi-Port) 10

Physical Layer Devices (Single-Port) 10

Pin Capacitance 218

Pin Descriptions 21

PIN DESIGNATIONS 19

PIN DESIGNATIONS (PQL144 15

PIN DESIGNATIONS (PQL144) 13

PIN DESIGNATIONS (PQR160) 14

listed by Group 17

PMD Interface 222

PMD Interface Timing (PECL) 222

PME 23

Polling 59

Power Good 23, 26

Power Management Event 23

Power Management Support 86

Power on Reset 94

Power Savings Mode 86

Power Supply Current 218, 221

Power Supply Pins 27

PQL144 232

PQR160 233

Preemption During Burst Transaction 45, 47

Preemption During Non-Burst Transaction 45, 47

R

RAP

Register Address Port 109

RAP Register 108

RDRA and TDRA 196

Receive Address Match 69

Receive Carrier Sense 25

Receive Clock 25

Receive Data 25

Receive Data Valid 25

Receive Descriptor (SWSTYLE = 0) 197

Receive Descriptor (SWSTYLE = 2) 197

Receive Descriptor (SWSTYLE = 3) 197

Receive Descriptor Table Entry 61

Receive Descriptors 197

Receive Exception Conditions 69

Receive FCS Checking 69

Receive Frame Queuing 61

Receive Function Programming 67

Receive Operation 67

Receive Symbol Timing 78

Receive Timing 224, 230

Receive Watermark Programming 136

Register Administration for 10BASE-T PHY Device 80

Register Programming Summary 212

Register Summary 203

Re-Initialization 56

RELATED AMD PRODUCTS 10

REQ 22

Reserved Register

10BASE-T Carrier Status Register (Register 23)

186

10BASE-T Configuration Register (Register 22)

186

Reserved Registers

HPR8 - HPR15, HPR17 189

Reserved Registers (Registers 8-15, 18, 20-23, and

25-31) 183

Reset 23, 93

Reset Register 95

Reverse Polarity Detect 72

RLEN and TLEN 195

RLL 25 Coding Tree 79

RMD0 197, 198

RMD1 198

RMD2 199

RMD3 200

ROMTNG Programming Values 154

RST 23

Running Registers 99

RWU 24

RX_CLK 25

RX_DV 25

RX_ER 25

Am79C978A

Index-7

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