AN53 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Lista de partido

AN53

The CS5322 Digital Filter

Unspecified 

CS5322 Filter

Output Word Rate(Hz)

(CLKIN = 1.024 MHz)

4000

2000

1000

500

250

125

62.5

-3dB Bandwidth (Hz)

1652.3

824.3

411.9

205.9

102.9

51.5

25.7

* Modulator and Filter Combination; limited by the modulator

Dynamic Range* (dB)

103

118

120

123

126

128

130

Table 1 CS5322 Filter Bandwidth Selections

Most general purpose processors, whether they

be fixed-point, or floating point, use a central

ALU (Arithmetic Logic Unit), through which all

processing occurs.

The CS5322 is a "signal processing chip" which

performs a dedicated FIR low pass filter

function. Figure 1 illustrates the block diagram

of the CS5322. When the CS5322 is operated

from a 1.024 MHz clock, the filter provides

seven deferent selectable decimation rates as

shown in Table 1. The -3 dB bandwidth of each

decimation rate is approximately 82% of the

nyquist frequency. The filter achieves a

minimum of 130 dB attenuation at the nyquist

frequency for all filter selections.

The filter offers selection of any one of seven

filter frequencies by means of hardware pins on

the chip or by means of writing a control word

into the configuration register via the serial port.

The CS5322 is architecturally quite different

from a general purpose DSP. The CS5322

contains three FIR filter stages. The 256 kHz

1-bit stream from the modulator enters FIR1 and

is multiplied by 33 11-bit coefficients. The bit

stream is decimated by eight as it is processed

and the output data is placed in RAM. FIR2 and

FIR3 are executed using a common multiplier.

FIR2 is a 13 coefficient (24-bit) variable

decimation stage. FIR2 can be programmed to

decimate at rates of 4, 8, 16, 32, 64, 128, and

256. Computations for FIR2 are processed in a

low power 24-bit by 24-bit multiplier and

accumulated in eight successive 50-bit

accumulators. The decimation rate is controlled

by the choice of which of the accumulators feeds

back to the multiplier. The output of FIR2 is

then processed by the 24-bit by 24-bit multiplier

and accumulated in a ninth 50-bit accumulator.

The decimate by 2 output result of FIR3 is

placed into the 24-bit serial port register in two’s

complement format.

Each of the seven filter output selections is

designed to ensure that, given an impulse input,

that one of the output words will provide a

sample point at the peak of the impulse

response. Because of this design feature, the

clock cycle lengths of each of the actual seven

filters are not binary multiples of each other.

Instead, the filters are designed to buffer input

data (each filter has a different buffer length to

ensure it provides a sample at the impulse peak)

to facilitate proper operation. The filter is

designed that to the user the filters actually take

c1(1)=0.0d0

c1(2)=0.0d0

c1(3)=1.0d0

c1(4)=4.0d0

c1(5)=10.0d0

c1(6)=20.0d0

c1(7)=35.0d0

c1(8)=56.0d0

c1(9)=84.0d0

c1(10)=120.0d0

c1(11)=161.0d0

c1(12)=204.0d0

c1(13)=246.0d0

c1(14)=284.0d0

c1(15)=315.0d0

c1(16)=336.0d0

c1(17)=344.0d0

c1(18)=336.0d0

c1(19)=315.0d0

c1(20)=284.0d0

c1(21)=246.0d0

c1(22)=204.0d0

c1(23)=161.0d0

c1(24)=120.0d0

c1(25)=84.0d0

c1(26)=56.0d0

c1(27)=35.0d0

c1(28)=20.0d0

c1(29)=10.0d0

c1(30)=4.0d0

c1(31=1.0d0

c1(32)=0.0d0

c1(33 =0.0d0

Table 2. FIR1 Filter Coefficients

2

AN53REV2

Share Link: