APU3046 Ver la hoja de datos (PDF) - Advanced Power Electronics Corp

Número de pieza

componentes Descripción

Lista de partido

APU3046

DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER

Advanced Power Electronics Corp 

APU3046

PIN#

10,15

11,14

12

13

17

18

19

20

22

23

24

PIN SYMBOL

HDrv2, HDrv1

LDrv2, LDrv1

PGnd

VCL

VccLDO

VOUT3

Fb3

SS

VSEN33

PGood

Gnd

PIN DESCRIPTION

Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,

from these pins to ground for the application when the inductor current goes negative

(Source/Sink), soft-start at no load and for the fast load transient from full load to no load.

Output driver for the synchronous power MOSFET.

This pin serves as the separate ground for MOSFET’s driver and should be connected to

the system’s ground plane. A high frequency capacitor (0.1 to 1mF) must be connected

from Vcc, VCL, VcH1 and VcH2 pins to this pin for noise free operation.

Supply voltage for the low side output drivers.

Separate input supply for LDO controller.

Driver signal for the LDO’s external transistor.

LDO’s feedback pin, connected to a resistor divider to set the output voltage of LDO.

This pin provides soft-start for the switching regulator. An internal current source charges

an external capacitor that is connected from this pin to ground which ramps up the output

of the switching regulator, preventing it from overshooting as well as limiting the input

current. The converter can be shutdown by pulling this pin below 0.5V.

Sense the LDO input voltage for UVLO.

Power good pin. This pin is a collector output that switches Low when any of the outputs

are outside of the specified under voltage trip point.

Analog ground for internal reference and control circuitry. Connect to PGnd with a short

trace.

BLOCK DIAGRAM

Vcc 4

10K

VSEN33 22

25uA

SS 20

POR

25K

1.25V

25K

Fb1 21

Comp1 5

Rt 7

Sync 8

VREF 1

1.25V

25K

Vp2 2

25K

Fb2 3

Fb2 Monitor Shut Down

Comp2 6

64uA Max

Error Amp1

Error Amp2

Bias

Generator

Vsen33

VcH1

VcH2

VccLDO

4.2V / 4.0V

2.5V / 2.3V

3.5V / 3.3V

3.5V / 3.3V

4.2V / 4.0V

PWM Comp1

UVLO

3V

1.25V

POR

S

Ramp1

Ramp2

Two Phase

Oscillator

Q

Set1 R

Reset Dom

Set2

SS>2V

PWM Comp2

0.5V

S

Q

R

Reset Dom

Fb1

PGood

Fb2

Fb3

POR

25K

1.25V

25K

Fb3 19

2V

40mA LDO Controller

SS

Figure 2 - Block diagram of the APU3046.

16 VcH1

15 HDrv1

13 VCL

14 LDrv1

9 VcH2

10 HDrv2

11 LDrv2

12 PGnd

23 PGood

17 VccLDO

18 VOUT3

24 Gnd

4/18

Share Link: