APW7067N Ver la hoja de datos (PDF) - Anpec Electronics
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APW7067N Datasheet PDF : 24 Pages
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APW7067N
Application Information
Output Voltage Selection
The output voltage of PWM converter can be programmed
with a resistive divider. Use 1% or better resistors for the
resistive divider is recommended. The FB pin is the
inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
VOUT1
=
0.8
×
1+
R1
RGND1
Where R1 is the resistor connected from VOUT1 to FB and
R is the resistor connected from FB to GND.
GND1
The linear regulator output voltage VOUT2 is also set by
means of an external resistor divider. The FBL pin is the
inverter input of the error amplifier, and the reference
voltage is 0.8V. The output voltage is determined by:
VOUT2
=
0.8 × 1+
R4
RGND2
Where R4 is the resistor connected from VOUT2 to FBL
and R is the resistor connected from FBL to GND.
GND2
Linear Regulator Input/Output Capacitor Selection
The input capacitor is chosen based on its voltage rating.
Under load transient condition, the input capacitor
will momentarily supply the required transient current. The
output capacitor for the linear regulator is chosen to
minimize any droop during load transient condition. In
addition, the capacitor is chosen based on its voltage
rating.
Linear Regulator Input/Output MOSFET Selection
The maximum DRIVE voltage is about 10V when VCC12 is
equal 12V. Since this pin drives an external N-channel
MOSFET, therefore the maximum output voltage of the
linear regulator is dependent upon the V .
GS
VOUT2MAX = 10 - VGS
Another criterion is its efficiency of heat removal. The
power dissipated by the MOSFET is given by:
P = I x (V – V )
D OUT2
IN2
OUT2
Where IOUT2 is the maximum load current, VOUT2 is the
nominal output voltage.
In some applications, heatsink might be required to help
maintain the junction temperature of the MOSFET below
its maximum rating.
Linear Regulator Compensation Selection
The linear regulator is stable over all loads current.
However, the transient response can be further enhanced
by connecting a RC network between the FBL and DRIVE
pin. Depending on the output capacitance and load
current of the application, the value of this RC network is
then varied.
PWM Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB and VOUT1
should be added. The compensation network is shown
in Fig. 9. The output LC filter consists of the output
inductor and output capacitors. The transfer function of
the LC filter is given by:
GAINLC
=
s2
1+ s × ESR × COUT1
× L × COUT1 + s × ESR × COUT1
+1
The poles and zero of this transfer functions are:
FLC = 2 × π ×
1
L × COUT1
FESR
=
1
2 × π × ESR × COUT1
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
VPHASE
L
VOUT1
COUT1
ESR
Figure 6. The Output LC Filter
Copyright © ANPEC Electronics Corp.
14
Rev. A.3 - Mar., 2008
www.anpec.com.tw
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