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AD7729

Dual Sigma-Delta ADC with Auxiliary DAC

Analog Devices 

AD7729–SPECIFICATIONS1

(AVDD1 = AVDD2 = +3 V ؎ 10%; DVDD1 = DVDD2 = +3 V ؎ 10%; DGND = AGND =

0 V, fCLK = 13 MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; TA = TMIN to TMAX unless otherwise noted)

Parameter

AD7729A

Units

Test Conditions/Comments

REFERENCE

REFCAP

Absolute Voltage, VREFCAP

REFCAP TC

REFOUT

Absolute Voltage, VREFOUT

REFOUT TC

1.3 ± 5%

50

1.3 ± 10%

50

V min/max

ppm/°C typ

V min/max

ppm/°C typ

0.1 µF Capacitor Required from REFCAP to AGND

0.1 µF Capacitor Required from REFOUT to AGND

ADC CHANNEL SPECIFICATIONS

Resolution

ADC Signal Range

VBIAS

Differential Signal Range

Single-Ended Signal Range

Input Sample Rate

Output Word Rate

DC Accuracy

Precalibration Offset Error

Post Calibration Offset Error

Post Calibration Offset Error TC

Input Resistance (DC)

Input Capacitance

Dynamic Specifications

Dynamic Range

Signal to (Noise + Distortion)

Gain Error

Gain Match Between Channels

Filter Settling Time

Frequency Response

0 kHz–70 kHz

85 kHz

96 kHz

135 kHz

>170 kHz

Absolute Group Delay

Group Delay Between Channels

(0 kHz–96 kHz)

Coding

15

2 VREFCAP

VREFCAP/2 to (AVDD – VREFCAP/2)

VREFCAP to (AVDD – VREFCAP)

VBIAS ± VREFCAP/2

VBIAS ± VREFCAP

13

270.83

± 45

± 10

50

1.23

10

67

64

±1

± 0.5

± 0.2

47

± 0.05

–1

–3.0

–55

–55

23

5

Twos Complement

Bits

V p-p

Volts

Volts

V min/max

V min/max

MSPS

kHz

mV typ

mV max

µV/°C typ

MΩ typ

pF typ

dB typ

dB min

dB max

dB max

dB max

µs typ

dB max/min

dB max

dB max

dB max

dB max

µs typ

ns typ

RxON = 1

Differential

Single-Ended

For Both Positive and Negative Analog Inputs

For Positive Analog Inputs; Negative Analog Inputs = VBIAS

TC = Temperature Coefficient

Input Frequency = 67.7 kHz

Input Frequency = 67.7 kHz, wrt 1.3 V

Input Frequency = 67.7 kHz, wrt VREFCAP

Does Not Include Input Antialias RC Circuit

AUXILIARY CONVERTER2

Resolution

Output Range

Code 000

Offset Error

Code 3FF

Gain Error

DC Accuracy

Integral Nonlinearity

Differential Nonlinearity

Update Rate

Load Resistance

Load Capacitance

ISINK

Full-Scale Settling Time

LSB Settling Time

Coding

10

2/32 × VREFCAP

± 35

2 VREFCAP

–60

+100

±4

±2

540

10

50

50

4

2

Binary

Bits

V

mV max

V

mV min

mV max

LSB max

LSB max

kHz max

kΩ min

pF max

µA typ

µs typ

µs typ

Maximum Output for Specified Accuracy = AVDD –

0.2 V or 2.6 V, Whichever Is Lower

Guaranteed Monotonic to 9 Bits

See Figure 1

See Figure 1

–2–

REV. 0

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