AD7729 Ver la hoja de datos (PDF) - Analog Devices
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AD7729 Datasheet PDF : 16 Pages
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AD7729
Table II. Receive Section Signal Ranges
Baseband Section
VREFCAP
VREFOUT
ADC
ADC Signal Range
VBIAS
Differential Input
Single-Ended Input
Signal Range
Differential
Single-Ended
Signal Range
1.3 V ± 5%
1.3 V ± 10%
2 VREFCAP
VREFCAP/2 to (AVDD1 – VREFCAP/2)
VREFCAP to (AVDD1 – VREFCAP)
VBIAS ± VREFCAP/2
VBIAS ± VREFCAP
Table III. Auxiliary Section Signal Ranges
AUXDAC
Output Code
Code 000
Code 3FF
Signal Range
2/32 × VREFCAP
2 VREFCAP
TIMING CHARACTERISTICS (AVDD1 = AVDD2 = +3 V ؎ 10%; DVDD1 = DVDD2 = +3 V ؎ 10%; AGND = DGND = 0 V;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = –40؇C to +105؇C
Units
Description
AUXILIARY FUNCTIONS
Clock Signals
t1
t2
t3
t4
t5
t6
t10
t11
t12
t13
t14
t15
t16
t17
76
30.4
30.4
t1
0.4 × t1
0.4 × t1
20
10
15
0
0
15
10
t4 + 15
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns min
See Figure 2.
MCLK Period
MCLK Width Low
MCLK Width High
ASCLK Period. See Figures 4 and 6.
ASCLK Width Low
ASCLK Width High
ASDI/ASDIFS Setup Before ASCLK Low
ASDI/ASDIFS Hold After ASCLK Low
ASDOFS Delay from ASCLK High
ASDOFS Hold After ASCLK High
ASDO Hold After ASCLK High
ASDO Delay from ASCLK High
ASDIFS Low to ASDI LSB Read by ASPORT
Interval Between Consecutive ASDIFS Pulses
Receive Section
Clock Signals
t7
t8
t9
t18
t19
t20
t21
t22
t23
t24
t25
t1
0.4 × t1
0.4 × t1
20
10
15
0
0
15
10
t7 + 15
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns min
See Figures 5 and 7.
BSCLK Period
BSCLK Width Low
BSCLK Width High
BSDI/BSDIFS Setup Before BSCLK Low
BSDI/BSDIFS HoldAfter BSCLK Low
BSDOFS Delay from BSCLK High
BSDOFS Hold After BSCLK High
BSDO Hold After BSCLK High
BSDO Delay from BSCLK High
BSDIFS Low to ASDI LSB Read by BSPORT
Interval Between Consecutive BSDIFS Pulses
ASCLK = MCLK/(2 × ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz.
BSCLK = MCLK/(2 × BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz.
Specifications subject to change without notice.
–4–
REV. 0
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