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BD9206EFV Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza
componentes Descripción
Lista de partido
BD9206EFV Datasheet PDF : 13 Pages
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BD9206EFV
Timing chart
VCC
VSET
STBY
EN
VREG
3.0V
UVULVOLiOnt(ernal signa)l
TSTDSDin(ternalsigna)l
ILED
①②③④ ⑤
Technical Note
① VCC input.
VSET Setting
It moves to OFF mode due to STBY =
L -> H. 5VREG (VREG) start. Rising
time ms.
It becomes UVLO = H depending upon
VREG >3.0V, it moves to stand-by
mode. As for LED driver, it is ready
state.
LED Lighting with EN = L -> H .
LED lighting out with EN = H L
it is same with
Detecting TSD with Ta > 175,
LED lighting out
2.9V
Deleting TSD with Ta < 155,
LED lighting
LED lighting out with STBY,EN=HL
Detecting UVLO=L with VREG<2.9V
Fig..7
⑦ ⑧ ⑨ ⑩⑪
Please be careful about a current flowing to the VCC side via the diode for electrostatic breakdown protection if a
voltage is applied to STBY terminal or EN terminal earlier than to VCC terminal.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
7/12
2009.07 - Rev.A

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