BS62LV8001EC(2008) Ver la hoja de datos (PDF) - Brilliance Semiconductor
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BS62LV8001EC Datasheet PDF : 10 Pages
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LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
VCC
tCDR
Data Retention Mode
VDR≧1.5V
CE2
CE2≦0.2V
VIL
BS62LV8001
VCC
tR
VIL
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
1. Including jig and scope capacitance.
ALL INPUT PULSES
90%
10%
→←
Rise Time :
1V/ns
90%
10%
→←
Fall Time :
1V/ns
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tRC
tAVQX
tAA
tE1LQV
tACS1
tE2HQV
tACS2
tGLQV
tOE
tE1LQX
tCLZ1
tE2HQX
tCLZ2
tGLQX
tOLZ
tE1HQZ
tCHZ1
tE2LQZ
tCHZ2
tGHQZ
tOHZ
tAVQX
tOH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(VCC = 3.0~5.5V)
MIN. TYP. MAX.
55
--
--
CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
MIN. TYP. MAX.
70
--
--
--
--
55
--
--
70
(CE1) --
--
55
--
--
70
(CE2) --
--
55
--
--
70
--
--
25
--
--
30
(CE1) 10
--
--
10
--
--
(CE2) 10
--
--
10
--
--
10
--
--
10
--
--
(CE1) --
--
30
--
--
35
(CE2) --
--
30
--
--
35
--
--
25
--
--
30
10
--
--
10
--
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV8001
4
Revision 2.4
Oct.
2008
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