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BT867

Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder

Conexant Systems 

Bt860/861

Multiport YCrCb to NTSC/PAL /SECAM

1.0 Functional Description

1.1 Pin Descriptions

Table 1-1. Pin Assignments (2 of 3)

Pin Name I/O

Pin #

Description

OSD[7:0]

ALPHA[1:0]

TTXDAT

TTXREQ

ALTADDR

SID

SIC

DACA

DACB

DACC

DACD

DACE

DACF

FSADJ1

FSADJ2

VREF

COMP1

COMP2

VBIAS1

VBIAS2

GRAPHIC AND BLENDING PINS

I 40-39, 36-31

I 30-29

Dedicated graphic overlay port (TTL compatible.) Accepts pixel data in 8-bit YCrCb

4:2:2 format. Data is latched on the rising edge of the system clock(1) (2).

Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video

and graphic overlay data. Data is latched on the rising edge of the system clock(1) (2).

I 74

O 73

I/O 62

I/O 75

I 76

TELETEXT AND SERIAL CONTROL INTERFACE

Teletext data input (TTL compatible)(1).

Teletext request output (TTL compatible).

Alternate slave address input (TTL compatible). This pin is sampled immediately

following a power-up or pin reset. A logical 1 corresponds to write address of 0x88

and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A

and a read address of 0x8B. See Chapter 5.0, for more detail. This pin also provides

special SCART signals when register field SCART_SEL≠00.

Serial programming interface data input/output (TTL compatible). Data is written to

and read from the device via this serial bus.

Serial programming interface clock input (TTL compatible). The maximum clock rate is

400 kHz.

ANALOG VIDEO

O 59

O 58

O 57

O 44

O 43

O 42

I 53

48

O 49

O 54

47

O 56

45

DAC A output. See Table 3-9.

DAC B output. See Table 3-9.

DAC C output. See Table 3-9.

DAC D output. See Table 3-9.

DAC E output. See Table 3-9.

DAC F output. See Table 3-9.

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these

pins and AGND control the full-scale output current of the DACs. For standard

operation, use the nominal values shown under Recommended Operating

Conditions. FSADJ1 controls DACs A/B/C and FSADJ2 controls DACs D/E/F.

Voltage reference pin. A 1.0 µF ceramic capacitor must be used to decouple this pin

to AGND. The capacitor must be as close to the device as possible to keep lead

lengths to an absolute minimum.

Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to

VAA. The capacitor must be as close to the device as possible to keep lead lengths

to an absolute minimum.

DAC bias voltage. Use a 0.1 µF ceramic capacitor to bypass this pin to AGND; the

capacitor must be as close to the device as possible to keep lead lengths to an

absolute minimum.

D860DSA

Conexant

1-3

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