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BT867

Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder

Conexant Systems 

Bt860/861

Multiport YCrCb to NTSC/PAL /SECAM

2.0 Inputs and Timing

2.2 Digital Video Ports

2.2.1 The P Port

The P port can accept video data from a variety of digital video sources. It is

designed specifically to interface directly with commercial MPEG video decoders

and D1 digital video sources. The P port supports both ITU-R BT.601 timing

(HSYNC* and VSYNC* signals), and ITU-R BT.656 timing (SAV and EAV

codes).

Data on the P[7:0] pins can be treated as either video or overlay data,

controlled by the VIDEO_SEL (1A[3]) and OVRLAY_SEL (1A[4]) register bits

(see Figure 2-1). Data on this port must be presented in 8-bit YCrCb 4:2:2 digital

video format. The P[7:0] pins are latched using the system clock as configured

using register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).

2.2.2 The VID Port

The VID port is specially configured for broadcast video sources, such as from a

television tuner or local cable system. It can accept a 27 MHz YCrCb 4:2:2 video

stream at the same pixel rate as the other ports, or it can accommodate alternate

clock rates, such as the 8xFsc clock rate used by the Bt835 family of video

decoders. Since the time base for these sources is external to the system and

therefore asynchronous to the local pixel clock, the Bt860/861 provides a

mechanism that synchronizes these two domains. When using the VID port in

locking mode, the Bt860/861 immediately synchronizes its vertical timing to the

vertical timing presented on the VIDVACT pin, and gradually adjusts its

horizontal timing and clock rate to further synchronize with the VID port.

VIDCLK latches the incoming data into a FIFO, and data is extracted at the

appropriate pixel rate for internal processing.

The average active horizontal pixel count must be equal to the value

programmed into the HACTIVE register field. For example, the Bt835 generates

pixels at a rate of 14.32 Mpix/s when used for NTSC video capture, but the actual

valid pixel count per line is determined by the video mode required. For support

of 27 MHz streams, 720 valid pixels will be delivered per line. This configuration

is compatible with other video devices connected to the Bt860/861 and running

with a continuous pixel rate of 13.5 Mpix/s. The Bt860/861 will generate the

necessary video timing and pixel clock to act as master for the other video device.

The VID port can be configured as the video source by setting register bit

VIDEO_SEL (1A[3]) to 1. Data on this port must be presented in 8-bit YCrCb

4:2:2 digital video format.

2.2.3 The OSD Port

The OSD port is functionally very similar to the P port, except that it cannot decode

ITU-R BT.656 timing. As the overlay source, this port can be mixed with the video

stream using one of the alpha-mixing modes described in Section 2.2.5. While

intended as an overlay source, the OSD port can be configured to be the sole image

content by using the appropriate blend programming.

The overlay source is selected by setting register bit OVRLAY_SEL (1A[4])

to 1. Data on this port must be presented in 8-bit YCrCb 4:2:2 digital video

format. The OSD[7:0] pins are latched using the system clock as configured by

register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).

D860DSA

Conexant

2-3

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