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BT8110

High-Capacity ADPCM Processor

Unspecified 

2

2.0 Functional Description

2.1 Overview

Figure 2-1 and Figure 2-2 illustrate block diagrams for Bt8110 and Bt8110B,

respectively. The quantizer and reconstruction tables are stored in the external

(Bt8110) or internal (Bt8110B) ROM that holds the fixed parameter values and

lookup tables specified in the ADPCM algorithms. Both the encoder and decoder

paths through the ADPCM processor provide the conversion of a 64-kbps µ-law

or A-law PCM channel to and from a 16-, 24-, 32-, or 40-kbit/s ADPCM channel.

The logic is arranged in a serial architecture to take full advantage of time

sharing of common circuitry. In the encoder path, prior to the conversion of the

PCM input to uniform PCM, a difference signal is obtained by subtracting an

estimate of the input signal from the input signal itself. An adaptive 3-, 7-, 15-, or

31-level quantizer (or 4-, 8-, or 16-level for embedded codes) is used to assign

two, three, four, or five binary digits, respectively, to the value of the difference

signal for transmission. An inverse quantizer produces a quantized difference

signal from the corresponding binary digits. The signal estimate is added to this

quantized difference signal to produce the reconstructed version of the input

signal. Both the reconstructed signal and the quantized difference signal are

operated upon by an adaptive predictor that produces the estimate of the input

signal, thereby completing the feedback loop.

The decoder path includes a structure identical to the feedback portion of the

encoder, together with a uniform PCM to µ-law or A-law conversion and

synchronous coding adjustment. The synchronous coding adjustment prevents

cumulative distortion occurring on synchronous tandem codings

(ADPCM-PCM-ADPCM... digital connections) under certain conditions. The

synchronous coding adjustment is achieved by adjusting the PCM output codes in

a manner that eliminates quantizing distortion in the next ADPCM encoding

stage.

100060C

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