BT8110 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Lista de partido

BT8110

High-Capacity ADPCM Processor

Unspecified 

2.0 Functional Description

2.4 Hardware Control

Bt8110/8110B

High-Capacity ADPCM Processor

2.4.1 Mode Pins

Mode Control (AD[2:0]) and Enable 32-Channel Operation (AD[3]) control pins

are fixed for a given operational configuration and are not subject to timing

specifications. Mode and control operation pins are defined in Table 2-5. The

enable 32-channel operation input is set high for 32- and 64-channel operation

and low for 24- and 48-channel operation.

Table 2-5. Mode Pins

AD[2]

AD[1]

AD[0]

Source

1

0

0

Interleaved

1

0

1

Encoder

1

1

0

Decoder

1

1

1

Only used for pre-Bt8110 design compatibility.

0

0

1

Interleaved Processor #1 48/64(1)

0

1

0

Interleaved Processor #2 48/64(1)

0

0

1

Encoder Processor #1 48/64(1)

0

1

1

Encoder Processor #2 48/64(1)

0

1

0

Decoder Processor #1 48/64(1)

0

0

0

Decoder Processor #2 48/64(1)

NOTE(S):

(1) See Appendix A for additional information.

2.4.2 Control Pins

Four pins control the coding (AD[6:4], ALE), one pin selects the PCM coding law

(WR*), and one pin selects transparent operation (CS). Figure 2-6 illustrates the

functional timing of these inputs. Figure 2-7 and Figure 2-8 detail encoder-only

operation and decoder-only operation, respectively.

The code select input pins have the same timing requirement as the parallel

signal inputs on PSIGEN. The transparent enable and A-law enable controls are

applied two clock cycles after the reset input and six clock cycles before the

coding input. Detailed timing requirements are provided in Chapter 4.0.

2-14

Conexant

100060C

Share Link: