ACE9050D Ver la hoja de datos (PDF) - Mitel Networks
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ACE9050D Datasheet PDF : 52 Pages
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ACE9050
ACEBus Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 1 85°C, VDD = 13·6V to 15·5V
Typical timings: TAMB = 125°C, VDD = 13·75V
Characteristic
Symbol
Min.
Value
Typ.
Max.
Units
Conditions
TRANSMIT
Clock high to Data bus driven
Data set-up time
Data hold time
Clock high to Latch high
Latch width 0 and 1
Latch width 3
Clock low
Clock high
Clock high to data line tristate
RECEIVE
Data set-up time
Data hold time
tCLHDA
491
ns
tDAVCLH
488
ns
tCLHDAI
491
ns
tCLHLAH
491
ns
tPW01
491
496
ns
tPW3
0·099
12·59
ms
tCLL
496
ns
tCLH
496
ns
tCLHDAZ
0
5
ns
tDAVCLL
14
ns
tCLLDAI
14
ns
Table 6 ACEBus Read and Write timings
Programmable width
SynthBus (Note: The SynthBus is not required when the ACE9050 is used as part of the ACE Chipset)
tD17VCLH
tCLH tCLL
SYNTHCLK
SYNTHDATA
DTFG
D1-7
D1-6
D3-1
tDAVCLH
tCLHDAI
D3-0
LATCH
tCLHLAH
tLAH
Fig.11 SynthBus timing diagram
SynthBus Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V
Typical timings: TAMB = 125°C, VDD = 13·75V
Characteristic
Symbol
Min.
Value
Typ.
Max.
Units
Conditions
First data bit set-up time
tD17VCLH
>0
7·84
µs
Data bit set-up time (except first) tDAVCLH
3·9
µs
Data hold time
tCLHDAI
4·0
µs
Clock high to latch high
tCLHLAH
4·97
µs
Latch width
tLAH
952
ns
Clock low
tCLL
3·99
µs
Clock high
tCLH
3·93
µs
Table 7 SynthBus timing
11
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