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ACE9050D

System Controller and Data Modem

Mitel Networks 

ACE9050

Associated register

BANK_SEL: Bank Select register (Write only)

Bit Name

Description

[7:5] - Not used

4 CS Chip Select:

1 = CSE2N

0 = CSEPN

3 BA 17 Banked Address A17 (see Table 27)

2 BA 16 Banked Address A16 (see Table 27)

1 BA 15 Banked Address A15 (see Table 27)

0 BA 14 Banked Address A14 (see Table 27)

Table 26

Bank_Sel Page Base Bank_Sel Page Base

3:0

Address (Hex)

3:0

Address (Hex)

0000

0001

0010

0011

0100

0101

0110

0111

00000

04000

08000

0C000

10000

14000

18000

1C000

1000

1001

1010

1011

1100*

1101*

1110*

1111*

20000

24000

28000

2C000

30000

34000

38000

3C000

*Refer to System Memory Map section for more details

Table 27

The banking is configured to occupy a 16K byte area of the

processor memory address space. It will thus create 16K byte

pages. This is configured in hardware and cannot be altered. It

is achieved by decoding the upper 2 bits of the processor

Address bus. If the address is in the range 8000H to BFFFH which

corresponds to A[15:14] = 10, the bank select circuit is invoked.

The bank addressing circuit only affects the upper four bits of the

external data bus. The top two A[17:16] are completely new, and

the next two A[15:14] are replacements for the processor A[15:

14] bits. Fig. 14 is a block diagram of the Bank Select circuitry.

AD15

AD14

5

ID [4:0]

EPROM

SELECT

VDD

17

16

15

14

CONTROL

1 = A, 0 = B

4

A[17:14]

ID[3:0]

BANK_SEL

REGISTER

ID4

4

A[17:14]

B

MUX

A

A

MUX

B

4 BA [17:14]

CSEPN

CSE2N

Fig. 14 Banked Addressing block diagram

20

The processor memory map is thus split into two distinct

areas: Non Banked address (Root) and Banked address:

Non Banked address area (Root)

A[17:14]: The address lines A[17:16] are set to 11. The

address lines A[15:14] are identical to the corresponding processor

address lines. This means the original area of the processor

memory map is mapped to the top of the external memory

address space.

CSE2N is never active, regardless of the value of the Bank_Sel

register bit 4. All access will be with CSEPN.

Banked Address area: A[17:14]

These address lines are the same as Bank Sel register bits

[3:0]. The programmer can in theory select up to 16 pages. This

is discussed in more detail in System Memory Map section.

CSE2N: The BANK SEL bit 4 determines whether this Chip

select line is enabled or the CSEPN.

Table 28 summarises operation in the two areas.

Address

area

A[17:16]

A[15:14] Chip Select

Non-Banked Set to 11

Same as

Micro

Always

CSEPN

Banked Bank Select register bits [3:0]

Bit 4

Table 28

Banked Address System Memory Map

The processor and the system memory map become different

because of the memory banking. The system memory map is

spit into 16K pages and the original processor Memory map

re-targeted. Refer to Fig. 15.

CPU

ADDRESS

15:0

0000

REGISTERS

RAM

1000

SYSTEM

ADDRESS



BANK 1

0XXXX

BANK 2

BANK 3

BANK 4

BANK 5

1XXXX

BANK 6



BANK 7

BANK 8

BANK 9

2XXXX

BANK 10

BANK 11



BANK 12

3XXXX

8000

BANKED

C000

FE00

BOOT ROM

FFFF

64K

PROCESSOR

MEMORY MAP

256K ROM

SYSTEM

MEMORY MAP

Fig. 15 Memory Map and Banked Addressing

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