CS4361-CZZ Ver la hoja de datos (PDF) - Cirrus Logic
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CS4361-CZZ Datasheet PDF : 24 Pages
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Confidential Draft
2/12/08
CS4361
4. APPLICATIONS
The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and
64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The
Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock
(SCLK) clocks audio data into the input data buffer.
4.1 Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed
mode is detected automatically during the initialization sequence by counting the number of MCLK transi-
tions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set
to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK, and
SCLK must be synchronous.
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x
-
-
-
-
-
-
8.1920
11.2896
12.2880
96x
128x
-
-
-
-
-
-
-
8.1920
-
11.2896
-
12.2880
12.2880
-
16.9344 22.5792
18.4320 24.5760
QSM
192x
-
-
-
12.2880
16.9344
18.4320
-
33.8680
36.8640
MCLK (MHz)
256x
384x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
-
-
22.5792 33.8680
24.5760 36.8640
32.7680 49.1520
-
-
-
-
DSM
512x
-
22.5792
24.5760
32.7680
-
-
-
-
-
768x 1024x
-
32.7680
33.8680 45.1580
36.8640 49.1520
49.1520
-
-
-
-
-
-
-
-
-
-
-
SSM
1152x
36.8640
-
-
-
-
-
-
-
-
Table 1. Common Clock Frequencies
4.2 Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external
and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1
External Serial Clock Mode
The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on
the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial
Clock Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock
Mode if no low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of
LRCK. Refer to Figure 12.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode al-
lows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.
12
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