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CS4361-CZZ

20-Pin, 24-Bit, 192 kHz, 6-Channel D/A Converter

Cirrus Logic 

Confidential Draft

2/12/08

CS4361

LRCK

SCLK

Left Channel

Right Channel

SDATA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Internal32SclCockLs K Mode

Right-Justified, 16-Bit Data

INT SCLK = 32 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

External SCLK Mode

Right-Justified, 16-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 32 Cycles per LRCK Period

Figure 10. CS4361 Data Format (Right-Justified 16)

4.3 De-Emphasis

The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam-

ple rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive

falling edges of LRCK. This function is available only in the internal Serial Clock Mode when LRCK < 50 kHz.

Gain

dB

T1=50 µs

0dB

-10dB

T2 = 15 µs

F1

3.183 kHz

F2 Frequency

10.61 kHz

Figure 11. De-Emphasis Curve (Fs = 44.1kHz)

4.4 Mode Select

Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after

RST is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in

Table 2.

Mode pin is:

Tied to VL

Tied to GND

Tied to LRCK

Tied to MCLK

Mode

I²S

Left-Justified

Right-Justified - 24 bit

Right-Justified - 16bit

Figure

7

8

9

10

Table 2. Mode Pin Settings

14

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