CDB4361 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4361 Datasheet PDF : 24 Pages
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Confidential Draft
2/12/08
CS4361
LRCK
Left Channel
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Internal SCLK Mode
External SCLK Mode
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I²S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 7. CS4361 Data Format (I²S)
LRCK
Left Channel
Right Channel
SCLK
SDATA
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Internal SCLK Mode
Left-Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
External SCLK Mode
Left-Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4361 Data Format (Left-Justified)
LRCK
SCLK
Left Channel
Right Channel
SDATA 0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
Interna3l2ScloCcksLK Mode
Right-Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
External SCLK Mode
Right-Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 9. CS4361 Data Format (Right-Justified 24)
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