CDB4361 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4361 Datasheet PDF : 24 Pages
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Confidential Draft
2/12/08
CS4361
4.5 Initialization and Power-Down
The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the pow-
er-down state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the
internal voltage reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are
powered down. The device will remain in the Power-Down Mode until RST is released and MCLK and LRCK
are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period
to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Final-
ly, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
USER: Apply Power
VQ and outputs
ramp down
Power-Down State
VQ and outputs low
VQ and outputs
ramp down
USER: Apply RST
or remove MCLK
USER: Apply MCLK, release RST
VQ and outputs ramp up
USER: Apply RST
or remove MCLK
USER: Remove
LRCK
Wait State
USER: Apply LRCK and MCLK
USER: Remove
LRCK
USER: change
MCLK/LRCK ratio
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
USER: No SCLK
SCLK mode = internal
Normal Operation
De-emphasis
available
USER: Applied SCLK
SCLK mode = external
Normal Operation
De-emphasis
not available
Analog Output
is Generated
Analog Output
is Generated
Figure 12. CS4361 Initialization and Power-Down Sequence
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