CS4385(2004) Ver la hoja de datos (PDF) - Cirrus Logic
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CS4385 Datasheet PDF : 56 Pages
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CS4385
3.2 Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are
continually scanned for any changes. These pins require connection to supply or ground as out-
lined in figure 8. For M0, M1, M2 supply is VLC and for M3 and M4 supply is VLS. Tables 4 - 6
show the decode of these pins.
In software mode the operational mode and data format are set in the FM and DIF registers.
See “Register Description” on page 37.
M1
(DIF1)
0
0
1
1
M4
0
0
0
0
1
1
1
M2
0
0
0
0
1
1
1
1
M0
(DIF0)
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
FORMAT
0
1
2
3
Table 4. PCM Digital Interface Format, Hardware Mode Options
FIGURE
9
10
11
12
M3
M2
DESCRIPTION
(DEM)
0
0
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
0
1
Single-Speed with 44.1kHz De-Emphasis; see Figure 20
1
0
Double-Speed (50 to 100 kHz sample rates)
1
1
Quad-Speed (100 to 200 kHz sample rates)
0
0
Auto Speed-Mode Detect (32kHz to 200kHz sample rates)
0
1
Auto Speed-Mode Detect with 44.1kHz De-Emphasis; see Figure 20
1
X
DSD Processor Mode (see Table 6 for details)
Table 5. Mode Selection, Hardware Mode Options
M1
M0
DESCRIPTION
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
1
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Direct Stream Digital (DSD), Hardware Mode Options
DS671A1
19
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