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CL-PD6833

PCI-to-CardBus Host Adapter

Cirrus Logic 

CL-PD6833

PCI-to-CardBus Host Adapter

2.3 Pin Descriptions

Table 2-1. PCI Bus Interface Pins

Pin Name

Description

Pin Number Qty. I/O Pwr. Drive

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

IDSEL

DEVSEL#

PERR#

PCI Bus Address / Data Input/Outputs: These pins 4–5, 7–12,

connect to PCI bus signals AD[31:0].

16–20, 22–24,

38–43, 45–46,

32

I/O

48–49, 51–56

PCI Bus Command / Byte Enables: The command

signalling and byte enables are multiplexed on the

same pins. During the address phase of a transaction,

C/BE[3:0]# are interpreted as the bus commands.

During the data phase, C/BE[3:0]# are interpreted as 13, 25, 36, 47 4

I/O

byte enables. The byte enables are valid for the

entirety of each data phase, and they indicate which

bytes in the 32-bit data path carry meaningful data for

the current data phase.

Cycle Frame: This signal, driven by current master,

indicates that a bus transaction is beginning. While

FRAME# is asserted, data transfers continue. When

27

FRAME# is deasserted, the transaction is in its final

phase.

1

I/O

Initiator Ready: This signal indicates the initiating

agent’s ability to complete the current data phase of

the transaction. IRDY# is used in conjunction with

29

TRDY#.

1

I/O

Target Ready: This signal indicates the target agent’s

ability to complete the current data phase of the trans-

30

action. TRDY# is used in conjunction with IRDY#.

1

I/O

Stop: This signal indicates the current target is

requesting the master to stop the current transaction.

32

1

I/O

Lock Transaction: This signal is used by a PCI mas-

ter to perform a locked transaction to a target memory.

LOCK# is used to prevent more than one master from

58

using a particular system resource.

1

I/O

Initialization Device Select: This input is used as a

chip select during configuration read and write trans-

a c t i o n s. T h i s i s a p o i n t - t o - p o i n t s i g n a l . T h e

CL-PD6833 must be connected to its own unique

15

IDSEL line (from the PCI bus arbiter or one of the

most-significant AD bus pins).

1

I

Device Select: When actively driven, this signal indi-

cates that it has decoded its own PCI address as the

target of the current access. As an input, DEVSEL#

31

indicates to the CL-PD6833 whether any device on

the bus has been selected.

1

I/O

Parity Error: The CL-PD6833 drives this output

active (low) if it detects a data parity error during a

33

write phase.

1

I/O

4

PCI

Spec.

4

PCI

Spec.

PCI

4 Spec.

PCI

4 Spec.

4

PCI

Spec.

4

PCI

Spec.

4

PCI

Spec

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4

PCI

Spec.

4

PCI

Spec.

June 1998

ADVANCE DATA BOOK v0.3

13

PIN INFORMATION

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