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CL-PD6833-QC-A

PCI-to-CardBus Host Adapter

Cirrus Logic 

CL-PD6833

PCI-to-CardBus Host Adapter

OVERVIEW (cont.)

The CL-PD6833 is compliant with the latest PC 97 and

PC 98 design guidelines. The CL-PD6833 is also

compliant with PCI 2.1, PCI 2.2 draft, PC Card

Standard (March 1997), ExCA™, and JEIDA 4.2

standards. Like the CL-PD6834, the register set of the

CL-PD6833 is a superset of the Intel® 365-SL, the

CL-PD672X, and the CL-PD6832 register sets; this

ensures full compatibility with existing card and socket

services software, thus maximizing PC software

compatibility.

The CL-PD6833 is compliant with the PCI Bus Power

Management Interface for PCI to CardBus Bridges,

which is the PCMCIA industry’s document for ACPI

compatibility. The device is also compliant with the PC

Card controller Device Class Specification.

The CL-PD6833 uses state-of-the-art clock control to

satisfy industry power consumption targets, thereby

assuring minimum power consumption during the

various operational and suspend states. The device

also offers a Hardware Suspend mode, which is a

method of powering down the host controller to the

minimum power consumption levels in addition to

ACPI-compatible power management features.

The ACPI-compatible power management features of

the CL-PD6833 plus its state-of-the-art clock

management and hardware suspend modes ensure

that the system designer is provided with all the power

management control needed to implement an energy-

efficient, mixed-voltage CardBus controller.

Zoomed video support had become an important con-

sideration for system designers since 1996. The

CL-PD6833 can be programmed to tristate its PC Card

interface so that graphics and audio signals from a

zoomed video–capable PC Card can be sent to the

respective graphics and audio controller zoomed video

ports. This solution is practical for multimedia applica-

tions such as DVD, full-motion video, and video confer-

encing.

The CL-PD6833 provides flexibility in non-PC

compatible applications by allowing easy translation of

PCI bus memory cycles to PC Card 16 I/O cycles for

processors with memory cycles only. In addition, the

CL-PD6833 has up to four multiplexed GPIO (general-

purpose I/O) pins to interface with external devices

that the system designer may wish to implement.

Package Outline Drawings

30.35 (1.195)

30.85 (1.215)

27.90 (1.098)

28.10 (1.106)

0.13 (0.005)

0.28 (0.011)

29.60 (1.165)

30.40 (1.197)

27.80 (1.094)

28.20 (1.110)

0.17 (0.007)

0.27 (0.011)

30.35 (1.195)

30.85 (1.215)

0.50

(0.0197)

BSC

CL-PD6833

208-PIN MQFP

27.90 (1.098)

28.10 (1.106)

25.50

(1.004)

REF

PIN 1 INDICATOR

PIN 208

PIN 1

25.50 (1.004) REF

0.40 (0.016)

0.75 (0.030)

3.17 (0.125)

3.67 (0.144)

1.30 (0.051) REF

29.60 (1.165)

30.40 (1.197)

0.50

(0.0197)

BSC

CL-PD6833

208-PIN LQFP

27.80 (1.094)

28.20 (1.110)

PIN 208

PIN 1

PIN 1 INDICATOR

0.45 (0.018)

0.75 (0.030)

1.35 (0.053)

1.45 (0.057)

1.00 (0.039) BSC

0.09 (0.004)

0.23 (0.009)

4.07

(0.160)

MAX

0.25

(0.010)

MIN

0° MIN

7° MAX

0.09 (0.004)

0.20 (0.008)

1.40 (0.055)

1.60 (0.063)

0.05 (0.002)

0.15 (0.006)

0° MIN

7° MAX

NOTES:

1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.

2) The drawing above does not reflect exact package pin count.

3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.

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