CL-PD6833-QC-A Ver la hoja de datos (PDF) - Cirrus Logic
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CL-PD6833-QC-A Datasheet PDF : 216 Pages
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CL-PD6833
PCI-to-CardBus Host Adapter
6. CARDBUS REGISTERS ...................................................................................................... 75
6.1 Status Event — PME_CXT .................................................................................................................. 75
6.2 Status Mask — PME_CXT................................................................................................................... 77
6.3 Present State ....................................................................................................................................... 78
6.4 Event Force .......................................................................................................................................... 80
6.5 Control — PME_CXT ........................................................................................................................... 82
7. OPERATION REGISTERS ................................................................................................... 85
7.1 Index .................................................................................................................................................... 85
7.2 Data...................................................................................................................................................... 90
8. DEVICE CONTROL REGISTERS........................................................................................ 91
8.1 Chip Revision ....................................................................................................................................... 91
8.2 Interface Status .................................................................................................................................... 92
8.3 Power Control — PME _CXT ............................................................................................................... 94
8.4 Interrupt and General Control — PME_CXT........................................................................................ 96
8.5 Card Status Change — PME_CXT ...................................................................................................... 98
8.6 Management Interrupt Configuration — PME_CXT............................................................................. 99
8.7 Mapping Enable .................................................................................................................................101
9. WINDOW MAPPING REGISTERS..................................................................................... 103
9.1 I/O Window Mapping Registers..........................................................................................................105
9.1.1 I/O Window Control ...............................................................................................................105
9.1.2 System I/O Map 0–1 Start Address Low ...............................................................................107
9.1.3 System I/O Map 0–1 Start Address High ..............................................................................107
9.1.4 System I/O Map 0–1 End Address Low ................................................................................108
9.1.5 System I/O Map 0–1 End Address High ...............................................................................108
9.1.6 Card I/O Map 0–1 Offset Address Low .................................................................................109
9.1.7 Card I/O Map 0–1 Offset Address High ................................................................................109
9.2 Memory Window Mapping Registers .................................................................................................110
9.2.1 System Memory Map 0–4 Start Address Low.......................................................................110
9.2.2 System Memory Map 0–4 Start Address High......................................................................111
9.2.3 System Memory Map 0–4 End Address Low ........................................................................112
9.2.4 System Memory Map 0–4 End Address High .......................................................................113
9.2.5 Card Memory Map 0–4 Offset Address Low .........................................................................114
9.2.6 Card Memory Map 0–4 Offset Address High ........................................................................115
10. GENERAL WINDOW MAPPING REGISTERS.................................................................. 117
10.1 General Mapping Registers for I/O Mode ..........................................................................................119
10.1.1 Gen Map 0–6 Start Address Low (I/O)..................................................................................119
10.1.2 Gen Map 0–6 Start Address High (I/O).................................................................................120
10.1.3 Gen Map 0–6 End Address Low (I/O) ...................................................................................121
10.1.4 Gen Map 0–6 End Address High (I/O) ..................................................................................122
10.1.5 Gen Map 0–6 Offset Address Low (I/O)................................................................................123
10.1.6 Gen Map 0–6 Offset Address High (I/O) ...............................................................................124
10.2 General Mapping Register for Memory Mode ....................................................................................125
10.2.1 Gen Map 0–6 Start Address Low (Memory) .........................................................................125
10.2.2 Gen Map 0–6 Start Address High (Memory).........................................................................126
10.2.3 Gen Map 0–6 End Address Low (Memory)...........................................................................127
10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128
10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129
10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130
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TABLE OF CONTENTS
ADVANCE DATA BOOK v0.3
June 1998
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