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CL-PS6700-VC-A Datasheet PDF : 48 Pages
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CL-PS6700
Low-Power PC Card Controller
2.2 PC Card Interface Signals
A PC Card socket can be configured as either memory only or combined I/O-memory. Some pins on the
PC Card interface have different meanings in memory and I/O modes. These pins are listed as dual-mode.
The mode is selected by a configuration register bit. When I/O mode is programmed, the CPU accesses
either I/O space or memory space on the card according to the upper address bits. The CPU Attribute
memory is accessible in either memory or I/O modes, again, selected by the upper address bits. A card
DMA device is accessible only in I/O mode.
2.2.1 Address and Data Signals
Signal
Type
Power
Source
Description
PCM_D[15:0] I/O
PCM_A[25:0] O
pcm PC Card data bus: Single-mode. Data transfer can be either byte or half-word (16-bit) as con-
figured by the CPU. All byte accesses are transferred through their natural byte lane only (odd
bytes on PCM_D[15:8] and even bytes on PCM_D[7:0]).
pcm PC Card address bus: Single-mode. This is a byte address during byte operations and a half-
word address during half-word (16-bit) accesses (that is, A[0] is kept low).
2.2.2 Access Control Signals
Signal
Type
Power
Source
Description
PCM_CE_L[2:1] O
PCM_OE_L
O
PCM_WE_L
O
pcm Card enables: Single-mode. These are the byte enable lines for the data bus.
PCM_CE_L[1] enables even bytes, D[7:0], and PCM_CE_L[2] enables odd bytes, D[15:8].
pcm Output enable for memory read data. Single-mode. PCM_OE_L enables the card’s data
outputs. During a write operation, this signal is deasserted (high). During a card read DMA
transfer, this signal is used as a terminal count and is asserted along with PCM_IORD_L
during the last DMA card read.
pcm Write enable signal for common memory and DMA: Single-mode. During a card write
DMA transfer, this signal is used as a terminal count and is asserted along with
PCM_IOWR_L during the last DMA card write.
CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED
14
PIN DESCRIPTIONS
November 1997
PRELIMINARY DATA BOOK v1.0

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