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CL-PS6700-VC-A

Low-Power PC Card Controller for the CL-PS7111

Cirrus Logic 

CL-PS6700

Low-Power PC Card Controller

2.2.5 Card Voltages and Reset Signals

Signal

Type

Power

Source

Description

PCM_VS[2:1] I/O

VDDhi Single-mode. These signals inform the host system of the voltage requirements and capabilities

of the card for reading its CIS before applying power to the card. This allows 3.3-V only cards

(which need not support 5-V operation during configuration). VS[2] primarily differentiates

between 3.3- and 5-V cards, while VS[1] primarily differentiates between 3.3-V and X.X-V

cards.

These signals, and the three power control signals, are bidirectional signals under software

control (register bits) for flexibility. All five signals are capable of generating interrupts. VS[2] can

also be configured to act as the card DREQ input.

PCTL[2:0]

I/O VDDhi Single-mode. These GPIO signals typically control the corresponding card’s power module or

switch. They determine the proper voltage for the VCC and/or the VPP pins of the socket. These

signals are directly controlled by register bits and thus, can control serially-controlled power

modules. They can also be programmed to transition to a new value automatically when the

PSLEEP_L input is asserted to automatically shut down card power in case of power fault con-

ditions. PCTL[2:0] are inputs during reset and therefore require an external pull-down or pull-up

resistor to avoid power being applied to the card socket.

PCM_RESET O

pcm Single-mode. This signal resets the PC Card, placing it into its default memory-only mode. The

signal remains in a high-impedance state after power-on or system reset. Cards that implement

the reset function pull up this signal with >100 kΩ. The CPU (after >1 ms) should pull this signal

low by writing a ‘0’ to bit 12 of the Card Interface Configuration register.

2.3 Power and Ground Pins

Signal

Group Description

V3V_Core

V3V_O

V5V_O

VDD_HI

VSS_Core

VSS_O

core

sys

pcm

VDDhi

Power to core logic; either 5 V or 3.3 V.

Power to system interface I/O buffers; either 5 V or 3.3 V, but must be the same as the CL-PS7111

power plane (V3V_Core).

Power to PC Card interface I/O buffers; either 5 V, 3.3 V, or 0 V.

This pin should be tied to the highest voltage in the system (as seen by CL-PS6700; either 5 V or 3.3

V).

Ground pins for the core and input buffers.

Ground pins for output buffers.

CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED

November 1997

PRELIMINARY DATA BOOK v1.0

17

PIN DESCRIPTIONS

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