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CS5360

24-Bit Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5360

Positive Digital Power - VD+

Pin 6, Input

Function:

Positive digital supply. Nominally +5 volts.

Master Clock - MCLK

Pin 7, Input

Function:

Clock source for the delta-sigma modulator sampling and digital filters. In Master Mode, the frequency of

this clock must be 256x the output sample rate, Fs. In Slave Mode, the frequency of this clock must be

either 256x, 384x or 512x Fs.

Serial Data Clock - SCLK

Pin 8, Input/Output

Function:

Clocks the individual bits of the serial data out from the SDATA pin. The relationship between LRCK,

SCLK and SDATA is controlled by DIF0 and DIF1.In Master Mode, SCLK is an output clock with a

frequency of 64x the output sample rate, Fs.In Slave Mode, SCLK is an input.

Serial Data Output - SDATA

Pin 9, Output

Function:

Two’s complement MSB-first serial data of 24 bits is output on this pin. Included in the serial data output

is the 8-bit Input Signal Level Bits. The data is clocked out via the SCLK clock and the channel is

determined by LRCK. The relationship between LRCK, SCLK and SDATA is controlled by DIF0 and

DIF1.

Peak Update - PU

Pin 11, Input

Function:

Transfers the Peak Signal Level contents of the Active Registers to the Output Registers on a high to

low transition on this pin. This transition will also reset the Active register.

Frame Signal - FRAME

Pin 10, Output

Function:

Frames the Peak Signal Level (PSL) Bits. FRAME goes high coincident with the leading edge of the first

PSL bit and falls coincident with the trailing edge of the last PSL bit as shown in Figures 8-10. A 47 kΩ

pull-down resistor on this pin will set the Peak Signal Level Monitoring format to "Bar Graph" mode.

Left/Right Clock - LRCK

Pin 12, Input/Output

Function:

LRCK determines which channel, left or right, is to be output on SDATA. The relationship between

LRCK, SCLK and SDATA is controlled by DIF0 and DIF1. Although the outputs for each channel are

transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. In

Master Mode, LRCK is an output clock whose frequency is equal to the output sample rate, Fs. In Slave

Mode, LRCK is an input clock whose frequency must be equal to Fs.

DS280PP2

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