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CS8920A

Crystal LAN ISA Plug-and-Play Ethernet Controller

Cirrus Logic 

CS8920A

data/address/control bus. On the network side, it

interfaces to the internal Manchester encoder/de-

coder (ENDEC). The primary functions of the

MAC are: frame encapsulation and decapsula-

tion; error detection and handling; and, media

access management.

Frame Encapsulation and Decapsulation

The CS8920A’s MAC engine automatically as-

sembles transmit packets and disassembles

receive packets. It also determines if transmit

and receive frames are of legal minimum size.

Transmission: Once the proper number of bytes

have been transferred to the CS8920A’s memory

(either 5, 381, 1021 bytes, or full frame), and

providing that access to the network is permitted,

the MAC automatically transmits the 7-byte pre-

amble (1010101b...), followed by the

Start-of-Frame Delimiter (SFD, 10101011b), and

then the serialized frame data. It then transmits

the Frame Check Sequence (FCS). The data after

the SFD and before the FCS (Destination Ad-

dress, Source Address, Length, and data field) is

supplied by the host. FCS generation by the

CS8920A may be disabled by setting the In-

hibitCRC bit (Register 9, TxCMD, bit C).

Figure 3.6 shows the Ethernet frame format.

Reception: The MAC receives the incoming

packet as a serial stream of NRZ data from the

Manchester encoder/decoder. It begins by check-

ing for the SFD. Once the SFD is detected, the

MAC assumes all subsequent bits are frame data.

It reads the DA and compares it to the criteria

programmed into the address filter (see Section

5.3 for a description of Address Filtering). If the

DA passes the address filter, the frame is loaded

into the CS8920A’s memory. If the BufferCRC

bit (Register 3, RxCFG, bit B) is set, the re-

ceived FCS is also loaded into memory. Once

the entire packet has been received, the MAC

validates the FCS. If an error is detected, the

CRCerror bit (Register 4, RxEvent, Bit C) is set.

Enforcing Minimum Frame Size: The MAC

provides minimum frame size enforcement of

both transmit and receive packets. When the

TxPadDis bit (Register 9, TxCMD, Bit D) is

clear, transmit frames will be padded with addi-

tional bits to ensure that the receiving station

receives a legal frame (64 bytes, including

CRC). When TxPadDis is set, the CS8920A will

not add pad bits and will transmit frames less

that 64 bytes. If a frame is received that is less

than 64 bytes (including CRC), the Runt bit

(Register 4, RxEvent, Bit D) will be set indicat-

ing the arrival of an illegal frame.

up to 7 bytes

1 byte

alternating 1s / 0s SFD

Packet

6 bytes

6 bytes

DA

SA

Frame

2 bytes

N bytes

M bytes 4 bytes

Optional Field LLC data Pad FCS

preamble

Direction of Transmission

frame length

min 64 bytes

max 1518 bytes

SFD = Start of Frame Delimiter

DA = Destination Address

SA = Source Address

LLC = Logical Link Control

FCS = Frame Check Sequence (also

called Cyclic Redundancy Check, or CRC)

Figure 3.6. Ethernet Frame Format

The optional field, which is two bytes long, is

either a TYPE field for Ethernet applications or

a LENGTH field for IEEE 802.3 applications.

The Pad field will be used only to get the frame

to the minimum size. When the CS8920 adds pad

bytes, the pad is the last byte of the LLC data

field repeated M times.

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DS238PP2

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