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CX5000

0.18um Structured ASIC

Unspecified 

CX5000:

0.18um Structured ASIC Product Family

♦ PCI, PCI-X, SSTL, HSTL, USB1.1, RSDS, LVPECL and LVDS up to 622Mbps

♦ 1.5V or 1.8V or mixed supply voltage operation

♦ Up to 1100 total pads

♦ Low-jitter analog PLL macros with internal loop filter

♦ Delay Lock Loop (DLL) macros for clock de-skewing

♦ Wide range of synthesizable IP cores such as CPUs and interface controllers

♦ Vast packaging library

♦ Standard ASIC tool flow

♦ Available front-end and FPGA conversion design services

♦ BIST and Scan synthesis test options

♦ Seamless migration to Standard Cell in high volume

♦ Excellent for SoC designs, new ASICs, and FPGA conversion

The CX5000 Structured ASIC “System Slice”

The CX5000 System Slice product line is designed to incorporate a mix of gates and memory optimized

for a wide range of today’s advanced SoCs. With a ratio of approximately 160% memory to gates, each

slice contains enough memory to support CPU cache, network rate-matching FIFOs, multiple video line

buffers and various other single- or dual-port applications.

The CX5000 System-Slice arrays shown in Table 1 have a variety of gate and memory counts. The

maximum usable gates in each array is design dependent and refers to the actual size of a customer

design prior to test insertion or timing closure.

BASE

ARRAY

CX50041

CX50101

CX50211

CX50331

CX50561

CX50841

CX51191

CX51761

TABLE 1.

CX5000 SYSTEM SLICE

MAX USABLE

ASIC GATES (K)

FAST BLOCK

SRAM (K)

30-40

64

91-101

160

131-144

364

207-228

518

336-369

880

526-578

1264

716-787

1774

1108-1219

2582

LOW JITTER

APLL/DLL

4/2

4/8

4/8

4/8

4/12

4/12

4/12

4/12

BOND

PADS

128

256

384

448

640

768

896

1152

There are a fixed number of block memories on each masterslice for speed, and for logic and memory

efficiency. Each slice has a total available memory count, which can be split into either 18K, 16K or 8K

blocks in a variety of widths and depths, or double-pumped to create smaller memories. The memory can

be configured as single- or dual-port RAM/ROM, as required.

ChipX uses the latest clock synthesis techniques during layout of the Structured ASIC. We provide the

user with four complete analog PLL units for clock phase alignment (when needed), frequency synthesis,

or stabilization. These PLL macros have excellent jitter performance and incorporate all of the analog

components needed for supply and loop filtering on board the masterslice. A DLL macro generator is

available for clock-edge alignment in timing-critical applications.

© ChipX Inc.

2

CEC034 (9/20/05)

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