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CXD2453Q

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2453Q

(e) Setting of operating mode, etc.

• VPOL, HPOL: These are used to set the polarity of VSYNC and HSYNC. A setting of "1" denotes positive

polarity, while a setting of "0" denotes negative polarity.

The default values are VPOL = 0, HPOL = 0.

• VSCN, HSCN: These are used to set the vertical and horizontal scanning directions of the LCD panel. VSCN

= 1 denotes downward scanning, while VSCN = 0 denotes upward scanning. HSCN = 1

denotes rightward scanning, while HSCN = 0 denotes leftward scanning. Setting data of

VSCN is output from the DWN (Pin 64), while setting data of HSCN is output from the RGT

(Pin 66).

The default values are VSCN = 0, HSCN = 1.

• SLXG, SLSX: These are used to set the input signals (operating mode). This IC has the following three

operating modes.

The default values are SLXG = 0, SLSX = 0.

Operating mode SLXG

XGA-I

0

XGA-II

1

S-XGA

X

SLSX

0

0

1

Note) X: Don't care

• HB, VB:

• SLLAP:

The XGA-I mode supports typical XGA signals. The XGA-II mode is for XGA signals in which

there is a low number of dots during a portion of the horizontal blanking period (typically when

HSYNC + back porch is 240 dots or less). Select the appropriate operating mode to satisfy the

conditions in the diagram on page 6 corresponding to the input signal. In the S-XGA mode,

1024 vertical lines are displayed decimating to 768 lines corresponding to the S-XGA signal

(1280 × 1024 dots).

These are used to switch the number of display dots on the LCD panel. The display is set to

960 dots horizontally when HB = 0, and to 640 lines vertically when VB = 0. The data of each

setting is output from the HB (Pin 62) and VB (Pin 61), respectively. Refer to the specifications

of the LCX017AL for details.

The default values are HB = 1, VB = 1.

This is used when the input signal clock and output signal clock differ such as when

converting the number of dots using a scan converter. When SLLAP = 1, only the serial data

interface and PLL counter of the IC internal circuits operate with CKI1 or CKI2 (clock

synchronized with input signal), while other sections operated with CKI3 or CKI4 (output

signal clock). When SLLAP = 0, all internal IC circuits operate with CKI1 or CKI2.

The default value is 0.

(f) Setting of IRACT fall/rise positions

• IRACT pulse

A pulse synchronized with HSYNC of the input signal can be output at any position and width. The fall position

of the pulse is set with IRD10 (MSB) through IRD0 (LSB), while the rise position is set with IRU10 (MSB)

through IRU0 (LSB). The values of IRD0 and IRU0 are ignored, and settings are made in 2-dot increments.

The setting range is from "0" to (N – 2). The same value cannot be set for IRD and IRU. Refer to the Timing

Chart for the relationship between setting values and pulse positions.

The default values are IRD10 through IRD0 = 00000000000, and IRU10 through IRU0 = 00010000000.

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