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CXD2453Q

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2453Q

(g) Setting of ORACT reset cycle/ORACT frequency division ratio

• ORACT pulses

ORACT pulses are completely identical to IRACT pulses when serial data SLLAP = 0, when SLLAP = 1, they

are generated by a dedicated counter (loop counter similar to the PLL counter) that operates according to an

independent clock (CKI3 or CKI4) different from the clock synchronized with input signal HSYNC (CKI1 or

CKI2). Since pulses for driving the LCD panel are also generated based on this counter at this time, the LCD

panel can be driven based on a clock and cycle that are different from the input signal. ORACT pulses are

synchronized with the cycle of the pulse for driving the LCD panel at this time, and can be output at any

position and width.

The frequency division ratio of the above dedicated counter is set with ORP10 (MSB) through ORP0 (LSB).

The value of (number of counter counts M) – 1 is the actual setting value. Only even numbers can be set for M,

and settings are made in 2 dot increments. The maximum setting is 2048 counts. This counter is reset with

VSYNC and HSYNC of a fixed cycle in order to synchronize it with the input signal, the interval of H at which it

is to be reset with this HSYNC is set with ORRS1 and ORRS0.

Setting data (ORRS1/ORRS0)

00

01

10

11

Reset cycle

Every 3H Every 4H Every 5H Every 1H

The default values are ORRS1 = 1, ORRS0 = 1, and ORP10 through ORP0 = 10100111111.

(h) Setting of ORACT fall/rise positions

The fall position of the ORACT pulse is set with ORD10 (MSB) through ORD0 (LSB), while the rise position of

the ORACT pulse is similarly set with ORU10 (MSB) through ORU0 (LSB). The values of ORD0 and ORU0 are

ignored, and settings are made in 2-dot increments. The setting range is from "0" to (M – 2). The same value

cannot be set for ORD and ORU. The relationship between setting values and pulse positions is as indicated

below.

The default values are ORD10 through ORD0 = 00000000000, and ORU10 through ORU0 = 00010000000.

HSYNC

(HSYNC when reset is applied to counter)

ORACT

8ck

(default setting)

128ck

ORD = 000/HEX

ORU = 080/HEX

• XHS pulse and XVS pulse

The XHS pulse is output over a width of 32 clocks 34 clocks after the fall of the IRACT pulse when SLLAP = 0.

The pulse has negative polarity. When SLLAP = 1, the pulse is similarly output over a width of 34 clocks after

the fall of the ORACT pulse.

The XVS pulse is VSYNC latched with the XHS pulse. Its polarity is always negative regardless of the polarity

of the input VSYNC.

• AC driving of LCD panels for no signal

When VSYNC has not been input for a specified period, a judgment of "no signal" is made to allow AC driving

of LCD panels even when there is no signal. A vertical start pulse and polarity inverted pulse (FRP) are output

at a specified cycle. The timing by which a judgment of "no signal" is made and the free running cycle are as

indicated below.

Operating mode

Free running detection timing (no signal period) and VST cycle during free running

All modes

1600H

– 13 –

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