7C1021BV-12 Ver la hoja de datos (PDF) - Cypress Semiconductor
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7C1021BV-12 Datasheet PDF : 11 Pages
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CY7C1021BV33
Switching Characteristics[4] Over the Operating Range
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
WRITE CYCLE[7]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5, 6]
tBW
Byte Enable to End of Write
Shaded areas contain advance information.
7C1021BV-8
Min. Max.
8
8
3
8
4
0
4
3
4
0
12
4
0
4
8
7
6
0
0
6
4
0
3
4
8
7C1021BV-10
Min. Max.
10
10
3
10
4
0
5
3
5
0
12
5
0
5
10
8
7
0
0
8
6
0
3
5
8
7C1021BV-12
Min. Max.
12
12
3
12
6
0
6
3
6
0
12
6
0
6
12
9
8
0
0
8
6
0
3
6
8
7C1021BV-15
Min. Max. Unit
15
ns
15 ns
3
ns
15 ns
7
ns
0
ns
7
ns
3
ns
7
ns
0
ns
15 ns
7
ns
0
ns
7
ns
15
ns
10
ns
10
ns
0
ns
0
ns
10
ns
8
ns
0
ns
3
ns
7
ns
9
ns
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
Description
Conditions[8]
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
tCDR[9]
tR[10]
Data Retention Current Com’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Chip Deselect to Data Retention Time
0
100
µA
ns
Operation Recovery Time
tRC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. No input may exceed VCC + 0.5V.
9. Tested initially and after any design or process changes that may affect these parameters.
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
Document #: 38-05148 Rev. *A
Page 4 of 11
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