7C1021BV-12 Ver la hoja de datos (PDF) - Cypress Semiconductor

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7C1021BV-12

64K x 16 Static RAM

Cypress Semiconductor 

Data Retention Waveform

VCC

3.0V

tCDR

CE

DATA RETENTION MODE

VDR > 2V

CY7C1021BV33

3.0V

tR

Switching Waveforms

[11, 12]

Read Cycle No. 1

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 (OE Controlled)[12, 13]

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

Notes:

11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

IISSBB

Document #: 38-05148 Rev. *A

Page 5 of 11

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