CY7C185-20PXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C185-20PXC Datasheet PDF : 15 Pages
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CY7C185
Switching Characteristics Over the Operating Range[4]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE1
tACE2
tDOE
tLZOE
tHZOE
tLZCE1
tLZCE2
tHZCE
tPU
tPD
Write Cycle[7]
tWC
tSCE1
tSCE2
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5]
CE1 LOW to Low Z[6]
CE2 HIGH to Low Z
CE1 HIGH to High Z[5, 6]
CE2 LOW to High Z
CE1 LOW to Power-up
CE2 to HIGH to Power-up
CE1 HIGH to Power-down
CE2 LOW to Power-down
Write Cycle Time
CE1 LOW to Write End
CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[5]
WE HIGH to Low Z
-15
-20
-35
Min Max Min Max Min Max Unit
15
20
35
ns
15
20
35
ns
3
5
5
ns
15
20
35
ns
15
20
35
ns
8
9
15
ns
3
3
3
ns
7
8
10
ns
3
5
5
ns
3
3
3
ns
7
8
10
ns
0
0
0
ns
15
20
20
ns
15
20
35
ns
12
15
20
ns
12
15
20
ns
12
15
25
ns
0
0
0
ns
0
0
0
ns
12
15
20
ns
8
10
12
ns
0
0
0
ns
7
7
8
ns
3
5
5
ns
Notes
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
6. At any temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal
can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *E
Page 5 of 15
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