CY7C4205V Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C4205V

64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

First Data Word Latency after Reset with Simultaneous Read and Write

CY7C4225V/4205V/4215V

CY7C4425V/4235V/4245V

WCLK

tDS

D0–D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

tFR[L18]

tSKEW2

tREF

EF

D3

D4

REN

Q0–Q17

OE

Empty Flag Timing

tOLZ

tA

tOE

tA [19]

D0

D1

WCLK

D0–D17

WEN

tDS

tENS

RCLK

EF

D0

tENH

tFRL[18]

tSKEW2

tREF

tDS

tENS

D1

tENH

tFRL[18]

tREF

tSKEW2

tREF

REN

OE

Q0–Q17

tA

D0

Notes:

18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK

+ tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

19. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06029 Rev. *C

Page 12 of 20

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