CY7C4205V Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C4205V

64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Empty Flag Timing

WCLK

tCLKH

WEN

PAE [20]

RCLK

REN

CY7C4225V/4205V/4215V

CY7C4425V/4235V/4245V

tCLKL

tENS tENH

tPAE

n+1 WORDS

IN FIFO

tPAE

tENS

n WORDS IN FIFO

Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)

WCLK

tCLKH

WEN

PAE

RCLK

REN

tCLKL

tENS tENH

tSKEW3 [22]

Note 21

tPAEsynch

N + 1 WORDS

INFIFO

tENS

tENS tENH

Note 23

tPAEsynch

Notes:

20. PAE offset − n. Number of data words into FIFO already = n.

21. PAE offset − n.

22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of

WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.

23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

Document #: 38-06029 Rev. *C

Page 14 of 20

Share Link: