CY8C20224 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8C20224 Datasheet PDF : 41 Pages
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
PSoC® Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU based system
components with one, low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
enables the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The PSoC architecture for this device family is comprised of
three main areas: core, system resources, and CapSense
analog system. A common, versatile bus enables connection
between I/O and the analog system. Each CY8C20x24 PSoC
device includes a dedicated CapSense block that provides
sensing and scanning control circuitry for capacitive sensing
applications. Depending on the PSoC package, up to 28 GPIOs
are also included. The GPIOs provide access to the MCU and
analog mux.
PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low-speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
12 MHz. The M8C is a 2-MIPS, 8-bit Harvard-architecture
microprocessor.
System resources provide additional capability, such as a
configurable I2C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The analog system is composed of the CapSense PSoC block
and an internal 1.8-V analog reference. Together, they support
capacitive sensing of up to 28 inputs.
CapSense Analog System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Figure 1. Analog System Block Diagram
IDAC
Vr
Reference
Buffer
C om parator
Mux
Mux
Refs
Cinternal
Cap Sense Counters
CSCLK
IMO
CapSense
Clock Select
Relaxation
O s c illator
(RO)
Analog Multiplexer System
The analog mux bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. The
analog multiplexer system in the CY8C20x24 device family is
optimized for basic CapSense functionality. It supports sensing
of CapSense buttons, proximity sensors, and a single slider.
Other multiplexer applications include:
■ Capacitive slider interface.
■ Chip-wide mux that enables analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal to noise signal level requirements application notes,
which are found in http://www.cypress.com > Design Resources
> Application Notes. In general, and unless otherwise noted in
the relevant application notes, the minimum signal-to-noise ratio
(SNR) requirement for CapSense applications is 5:1.
Document Number: 001-41947 Rev. *L
Page 3 of 41
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