D765 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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D765 Datasheet PDF : 17 Pages
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uPD765A/uPD765B
NEC
Pin Identification
No.
1
2
3
4
5
6-13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31, 32
33
34
Symbol
RESET
RD
WR
CS
A0
DB0-DB7
DRQ
DACK
TC
INDEX
INT
CLK
GND
WCLK
WINDOW
R DATA
SYNC
WE
MFM
SIDE
USn US1
WDATA
P S 0 PS1
FLT/TRK0
WPRT/2SIDE
35
READY
36
HDLD
37
FLTR/STEP
38
LCT/DIR
39
m/SEEK
40
kc
Function
Reset input
Read control input
Write control input
Chip select input
Data or status select input
Bidirectional data bus
DMA request output
DMA acknowledge input
Terminal count input
Index input
Interrupt request output
Clock input
Ground
Write clock input
Read data window input
Read data input
VCO sync output
Write enable output
MFM output
Head select output
FDD unit select output
Write data output
Preshift output
Fault/track zero input
Write protect/two side
input
R e a d y input
Head load output
Fault reset/step output
Low current direction
output
Read/write/ seek output
DC power ( +5 V)
Pin Functions
RESET (Reset)
The RESET input places the FDC in the idle state. It re-
sets the output lines to the FDD to 0 (low), except PSO, 1
and WDATA (undefined), INT and DRQ also go low;
DBO-7 goes to an input state. It does not affect SRT,
HUT, or HLT in the Specify command. If the RDY input is
held high during reset, the FDC will generate an inter-
rupt within 1.024ms. To clear this interrupt, use the
Sense Interrupt Status command.
RD (Read Strobe)
The RD input allows the transfer of data from the FDC
to the data bus when low and either CSor DACK is
asserted.
WR (Write Strobe)
TheWR input allows the transfer of data to the FDC
from the data bus when low. Disabled when CSis high.
A0 (Data/Status Select)
The A0 input selects the data register (A0 = 1) or status
register (A0=O) contents to be accessed through the
data bus.
CS(Chip Select)
The FDC is selected when CSis low, enabling RD and
WR.
DBo-DB7 (Data Bus)
DBo-DB7 are a bidirectional 8-bit data bus. Disabled
when CSis high.
DRQ (DMA Request)
The FDC asserts the DRQ output high to request a DMA
transfer.
DACK (DMA Acknowledge)
When the DACK input is low, a DMA cycle is active and
the controller is performing a DMA transfer.
TC (Terminal Count)
When theTC input is high, it indicates the termination of
a DMA transfer. It terminates data transfer during Read/
Write/Scan commands in DMA or interrupt mode.
INDEX (Index)
The INDEX input goes high at the beginning of a disk
track.
INT (Interrupt)
The INT output is FDC’s interrupt request. In Non-DMA
mode, the signal is output for each byte. In DMA mode,
it is output at the termination of a command operation.
CLK (Clock)
CLK is the input for the FDC’s single-phase, lTL-level
squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up
resistor.)
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